I try to get an UART IP core in combination with the NIOS2 (softcore) running on the Cyclone 10 LP evaluation board.
So far everything works fine in polling mode. However, I cannot manage to get the interrupts running on the softcore.
The FPGA is configured in the following way.
From the picture it can be seen, that the interrupt line is connected to the NIOS2 softcore processor.
The following picture shows that the Altera UART driver is available.
The initalization code provided by Altera looks like the following.
/*
* Initialize the interrupt controller devices
* and then enable interrupts in the CPU.
* Called before alt_sys_init().
* The "base" parameter is ignored and only
* present for backwards-compatibility.
*/
void alt_irq_init ( const void* base )
{
ALTERA_NIOS2_GEN2_IRQ_INIT ( NIOS2E, nios2e);
alt_irq_cpu_enable_interrupts();
}
/*
* Initialize the non-interrupt controller devices.
* Called after alt_irq_init().
*/
void alt_sys_init( void )
{
ALTERA_AVALON_JTAG_UART_INIT ( JTAG_UART, jtag_uart);
ALTERA_AVALON_UART_INIT ( UART_0, uart_0);
ALTERA_REMOTE_UPDATE_INIT ( REMOTE_UPDATE_0, remote_update_0);
}
To enable interrupts you have to disable the reduced drivers in the BSP Editor of NIOS2. One might assume, that if you connect the interrupt line in Quartus Prime this will be considered in the NIOS2EDS Project. Unfortunately this is not the case.
Related
I want to run an audio emulator of the genesis fm sound chip inside arduino. I plan to run it on a rp2040 which has plenty of power to run it
This is the emulator code:
https://github.com/nukeykt/Nuked-OPN2/blob/master/ym3438.h
And this is how Im trying to instantiate it, but I have errors. Can you point me on how to run the emulator?
#include "ym3438.h"
int buff = 0;
ym3438_t myChip;
void setup() {
}
void loop() {
buff++;
//this should advance the emultor clock
OPN2_Clock(myChip, buff);
//this should generate the sound samples
OPN2_Generate(myChip, buff);
}
Thanks!!
When trying to compile I get:
Compilation error: cannot convert 'ym3438_t' to 'ym3438_t*' for argument '1' to 'void OPN2_Clock(ym3438_t*, Bit16s*)'
I have tried putting* like:
OPN2_Clock(myChip*, buff*);
But it does not work either. Honesty Im not sure how to instantiate it
I am using mpu6050 for my project but it shows following error -
Testing device connections...
MPU6050 connection failed
this error is showed only when iI am trying to use object of MPU6050
but when I don't use instance of MPU6050 and use Wire library instead (like follow) it works -
Wire.begin(); // Initialize communication
Wire.beginTransmission(MPU); // Start communication with MPU6050 // MPU=0x68
Wire.write(0x6B); // Talk to the register 6B
Wire.write(0x00); // Make reset - place a 0 into the 6B register
Wire.endTransmission(true); //end the transmission
but I want to use this code -
mpu.initialize(); //start MPU
Serial.println(F("Testing device connections...")); //debugging serial statement
Serial.println(mpu.testConnection() ? F("MPU6050 connection successful") : F("MPU6050 connection failed"));
// supply your own gyro offsets here, scaled for min sensitivity
mpu.setXGyroOffset(0);
mpu.setYGyroOffset(0);
mpu.setZGyroOffset(0);
mpu.setZAccelOffset(1688);
please help me
I had the same problem.
The problem comes from those lines in the MPU6050.cpp file. You can find it in your sketchbook folder.
To do so: Open the Arduino IDE then File > Preferences > Sketchbook location.
//I2Cdev device library code is placed under the MIT license
//Copyright (c) 2012 Jeff Rowberg
/** Verify the I2C connection.
* Make sure the device is connected and responds as expected.
* #return True if connection is valid, false otherwise
*/
bool MPU6050::testConnection() {
return getDeviceID() == 0x34;
}
This is the getDeviceId function
//I2Cdev device library code is placed under the MIT license
//Copyright (c) 2012 Jeff Rowberg
/** Get Device ID.
* This register is used to verify the identity of the device (0b110100, 0x34).
* #return Device ID (6 bits only! should be 0x34)
* #see MPU6050_RA_WHO_AM_I
* #see MPU6050_WHO_AM_I_BIT
* #see MPU6050_WHO_AM_I_LENGTH
*/
uint8_t MPU6050::getDeviceID() {
I2Cdev::readBits(devAddr, MPU6050_RA_WHO_AM_I, MPU6050_WHO_AM_I_BIT, MPU6050_WHO_AM_I_LENGTH, buffer);
return buffer[0];
}
I just modified the testConnection function to return true, and it worked for me.
//I2Cdev device library code is placed under the MIT license
//Copyright (c) 2012 Jeff Rowberg
bool MPU6050::testConnection() {
return true;
}
The problem is that the device identifier is not 0x34 (in my case it is 0x39).
In order not to "cheat" I made the following change:
Comment out this line:
Serial.println(accelgyro.testConnection() ? "MPU6050 connection successful" : "MPU6050 connection failed");
And inserted these lines:
Serial.print("DeviceID: ");
Serial.println(accelgyro.getDeviceID());
So the program will write the device identifier instead of giving a response that it didn't find device 0x34.
I want to read the values of some Cortex-A53 registers, such as
D_AA64ISAR0_EL1 (AArch64)
ID_ISAR5 (Aarch32)
ID_ISAR5_EL1 (Aarch64)
Unfortunately, I lack a little embedded/assembly experience. The documentation reveals
To access the ID_AA64ISAR0_EL1:
MRS , ID_AA64ISAR0_EL1 ; Read ID_AA64ISAR0_EL1 into Xt
ID_AA64ISAR0_EL1[31:0] can be accessed through the internal memory-mapped interface
and the external debug interface, offset 0xD30.
I decided to utilize devmem2 on my target (since busybox does not include the devmem applet). Is the following procecure correct to read the register?
devmem2 0xD30
The part which I am unsure about is using the "offset" as a direct physical address. If it is the actual address, why call if "offset" and not "address". If it's an offset, what is the base address? I am 99% certain this is not the correct procedure, but how do I know the base address to add the offset to? I have searched the Armv8 technical reference manual and A53 MPCore documents to no avail. The explain the register contents in detail but seem to assume you read them from ASM using the label ID_AA64ISAR0_EL1.
Update:
I found this:
Configuration Base Address Register, EL1
The CBAR_EL1 characteristics are:
Purpose Holds the physical base address of the memory-mapped GIC CPU
interface registers.
But it simply duplicates my problem, how to read this other register?
Update 2:
The first update seems relevant only for GIC and not for configuration registers I am trying to read (I misunderstood the information I think).
For the specific problem at hand (checking crypto extension availability) one may simply cat /proc/cpuinfo and look for aes/sha etc.
Update 3:
I am now investigating http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0176c/ar01s04s01.html, as well as the base address being SoC specific and thus may be found in the reference manual of the SoC.
Update 4:
Thanks to the great answer I seem to be able to read data via my kernel module:
[ 4943.461948] ID_AA64ISA_EL1 : 0x11120
[ 4943.465775] ID_ISAR5_EL1 : 0x11121
P.S.: This was very insightful, thank you again!
Update 5:
Source code as per request:
/******************************************************************************
*
* Copyright (C) 2011 Intel Corporation. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
* the GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
*
*****************************************************************************/
#include <linux/module.h>
#include <linux/types.h>
/*****************************************************************************/
// read system register value ID_AA64ISAR0_EL1 (s3_0_c0_c6_0).
static inline uint64_t system_read_ID_AA64ISAR0_EL1(void)
{
uint64_t val;
asm volatile("mrs %0, ID_AA64ISAR0_EL1" : "=r" (val));
return val;
}
// read system register value ID_ISAR5_EL1 (s3_0_c0_c2_5).
static inline uint64_t system_read_ID_ISAR5_EL1(void)
{
uint64_t val;
asm volatile("mrs %0, s3_0_c0_c2_5" : "=r" (val));
return val;
}
/*****************************************************************************/
int init_module(void)
{
printk("ramdump Hello World!\n");
printk("ID_AA64ISAR0_EL1 : 0x%llX\n", system_read_ID_AA64ISAR0_EL1());
printk("ID_ISAR5_EL1 : 0x%llX\n", system_read_ID_ISAR5_EL1());
return 0;
}
void cleanup_module(void)
{
printk("ramdump Goodbye Cruel World!\n");
}
MODULE_LICENSE("GPL");
Disclaimer: I am not an Aarch64 expert, but I am currently learning about the architecture and have read a bit.
You cannot read ID_AA64ISAR0_EL1, ID_ISAR5_EL1 nor ID_ISAR5 from a user-mode application running at EL0: the _EL1 suffix means than running at least at EL1 is required in order to be allowed to read those two registers.
You may find helpful to read the pseudo-code in the arm documentation here and here.
In the case of ID_ISAR5 for example, the pseudo-code is very explicit:
if PSTATE.EL == EL0 then
UNDEFINED;
elsif PSTATE.EL == EL1 then
if EL2Enabled() && !ELUsingAArch32(EL2) && HSTR_EL2.T0 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HSTR.T0 == '1' then
AArch32.TakeHypTrapException(0x03);
elsif EL2Enabled() && !ELUsingAArch32(EL2) && HCR_EL2.TID3 == '1' then
AArch64.AArch32SystemAccessTrap(EL2, 0x03);
elsif EL2Enabled() && ELUsingAArch32(EL2) && HCR.TID3 == '1' then
AArch32.TakeHypTrapException(0x03);
else
return ID_ISAR5;
elsif PSTATE.EL == EL2 then
return ID_ISAR5;
elsif PSTATE.EL == EL3 then
return ID_ISAR5;
One easy way to read those register would be to write a tiny loadable kernel module you could call from your user-mode application: Since the Linux kernel is running at EL1, it is perfectly able to read those three registers.
See for example this article for a nice introduction to Linux loadable kernel modules.
And this is likely that an application running at EL0 cannot access memory-mapped registers accessible only from EL1, since this would obviously break the protection scheme.
The C code snippets required to read those registers in Aarch64 state would be (tested with gcc-arm-9.2-2019.12-x86_64-aarch64-none-linux-gnu) :
#include <stdint.h>
// read system register value ID_AA64ISAR0_EL1 (s3_0_c0_c6_0).
static inline uint64_t system_read_ID_AA64ISAR0_EL1(void)
{
uint64_t val;
asm volatile("mrs %0, s3_0_c0_c6_0" : "=r" (val));
return val;
}
// read system register value ID_ISAR5_EL1 (s3_0_c0_c2_5).
static inline uint64_t system_read_ID_ISAR5_EL1(void)
{
uint64_t val;
asm volatile("mrs %0, s3_0_c0_c2_5" : "=r" (val));
return val;
}
Update #1:
The GCC toolchain does not understand all arm system register names, but can nevertheless properly encode system registers access instructions if specified which exact values of the coproc, opc1, CRn, CRm, and opc2 fields are associated to this register.
In the case of ID_AA64ISAR0_EL1, the values specified in the Arm® Architecture Registers Armv8, for Armv8-A architecture profile document are:
coproc=0b11, opc1=0b000, CRn=0b0000, CRm=0b0110, opc2=0b000
The system register alias would then be s[coproc]_[opc1]_c[CRn]_c[CRm]_[opc2], that is s3_0_c0_c6_0 in the case of ID_AA64ISAR0_EL1.
I see this tool maybe meets your need:
system-register-tools
It just provides reading and writing system registers function for arm64, likes MSR-tools in x86.
I'm facing problem with sending AT Commands using Arduino Uno. I've written a small program (link below) to set up a server. I need to send data to Atmega from my laptop using Wifi module ESP8266. Everything would be fine if the entire program would do at once at the moment I need to comment and uncomment (adding and removing double slashes) every line of AT code, because only one AT command executes in a single compilation.
It seems like the program gets stuck somewhere in the while-loop (even on the module, I can see that blue diode stops blinking). I think that I've done something wrong in code and I would appreciate any help.
#include <SoftwareSerial.h>
SoftwareSerial espmod(2, 3);
void commands(String cmd, int waittime);
void setup(void) {
Serial.begin(9600);
espmod.begin(9600);
while (!Serial) {;}
commands("AT+GMR\r\n", 1000);
commands("AT+RST\r\n", 500);
commands("AT+CWMODE=1\r\n", 500);
commands("AT+CWJAP=\"SSID\",\"PASS\"\r\n", 4000);
commands("AT+CIPMUX=1\r\n", 500);
commands("AT+CIPSERVER=1,333\r\n", 500);
commands("AT+CIFSR\r\n", 500);
}
void loop() { // run over and over
}
void commands(String cmd, int waittime) {
espmod.print(cmd);
delay(waittime);
while(espmod.available()) {
char val = espmod.read();
Serial.write(val);
}
}
Here's the screen:
Version:
AT Version: 0.21.0.0
SDK Version: 0.9.5
Connections:
ESP
VCC -- 3,3 V (external source)
GND -- GND -- Arduino GND
RX -- TX (Arduino pin 3)
TX -- RX (Arduino pin 2)
CH_PD -- 3,3 V
RST -- 3,3 V
EDIT:
I've been fighting with this for couple of days, still without solution, but today it worked finally, but only once (after reseting power supply it's still the same) ! I could've seen all commands doing on SerialMonitor, so there is everything fine with code and i guess there is something wrong with esp module. As far as i can get only one AT command sent and executed in a single compilation, is it possible that 0,5 A current i provide to the module is not enough? Can module be out of the memory ? Is there any way to see SoftwareSerial monitor (is there anything like that)?
There is an unnecessary loop in command function. Let the arduino handle the loop for you. Also it is better to try with different delay parameters, maybe you can decrease some. Here the code I offer :
void loop() {
while (espmod.available()){
String result = espmod.readStringUntil('\n');
Serial.println("AT result : " + result);
}
}
void commands(String cmd, int waittime) {
espmod.print(cmd);
delay(waittime);
}
I am trying to print sigset using printf. In this program, I have used sigprocmask to block SIGHUP and SIGTERM. After initializing set and oset to empty sets, they are giving some random hex strings as output. How should I solve this problem??
Also, I have a doubt regarding the expected output of this program if I press Ctrl-C after execution. Does the catcher function also inherit the present signal set and should print the same as set??
#include<stdio.h>
#include<unistd.h>
#include<signal.h>
#include<bits/sigset.h>
void catcher(int sig){
sigset_t set;
sigprocmask(SIG_SETMASK, NULL, &set);
printf("%x inside function\n",set);
}
int main()
{
sigset_t set,oset;
signal(SIGINT,catcher);
sigemptyset(&set);
sigemptyset(&oset);
printf("%x\n",oset);
printf("%x\n",set);
sigaddset(&set,SIGHUP);
sigaddset(&set,SIGTERM);
sigprocmask(SIG_SETMASK,NULL,&oset);
printf("%x\n",oset);
printf("%x\n",set);
sigprocmask(SIG_BLOCK,&set,&oset);
pause();
sigprocmask(SIG_SETMASK,&oset,&set);
printf("%x\n",set);
}
Manual says :
The sigprocmask() function examines and/or changes the current signal
mask (those signals
that are blocked from delivery). Signals are blocked if they are members of the current
signal mask set.
This mask is for the whole process, and is used to block some signals for delivery. There is no inheritence here. There is a mask that describe at each execution point the set of blocked signals.
What you should know is that by default when a signal is catched, it is automatically added to the set of blocked signals (to prevent reentrance to the catching routine), and removed at the end of it.
An execution of your code on my machine gives :
0 // empty set
0 // empty oset
0 // empty oset
4001 // set = { HUP, TERM }
^C4003 // in catcher, signal is automatically blocked set={HUP, INT, TERM}
4001 // after catcher back in old state set={HUP,TERM}
That means that bit 0 and 14 are used for SIGHUP and SIGTERM, and bit 1 for SIGINT, which is exactly what I found in my system header file :
#define SIGHUP 1 /* hangup */
#define SIGINT 2 /* interrupt */
#define SIGTERM 15 /* software termination signal from kill */