How does Intel DSA (Data Streaming Accelerators) can store the descriptors in the local sram? - intel

I would like to ask a question regarding to Intel DSA (Data Streaming Accelerator).
According to the documentation, Intel DSA can support up to 256 queues and 65536 entries(the bit width of registers are 8 and 16 respectively). Are all descriptors stored locally in the sram, or is the hardware written to the DDR?
I think such a large number of descriptors and queues will take up a lot of chip area, and the hardware circuit timing and congestion is difficult to control.

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SNMP Network traffic difference between 32-bit and 64-bit Counter

I try to monitor some Cisco 2960x Switch devices and I know there are the SNMP OID's ifInOctets (32-bit Counter) and ifHCinOctets (64-bit Counter). Can someone explain me whats the difference between those Counters and which one I should use for a GigabitEthernet Interface?
Thanks
64-bit counters are used for high capacity interfaces where 32-bit counters do not provide enough capacity and wrap too fast.
As the speed of network media increases, the minimum time in which a 32-bit counter wraps decreases.
For example, a 10 Mbps stream of back-to-back, full-size packets causes ifInOctets to wrap in just over 57 minutes. At 100 Mbps, the minimum wrap time is 5.7 minutes, and at 1 Gbps, the minimum is 34 seconds.
For interfaces that operate at 20,000,000 (20 million) bits per second or less, you must use 32-bit byte and packet counters. For interfaces that operate faster than 20 million bits per second, and slower than 650,000,000 bits per second, you must use 32-bit packet counters and 64-bit octet counters. For interfaces that operate at 650,000,000 bits/second or faster, 64-bit packet and octet counters must be used.
You can check the following link for detailed explanation on SNMP counters.

Can Intel Xeon Phi get data direct from another PCI device?

Can Intel Xeon Phi be configured to receive data direct from FPGA board, process them and send result to host memory?
I have large flow of input data and don't want to have redundant transfers (FPGA board ->Host Memory->MIC->Host Memory) over PCI. I want more elegant scheme (FPGA board-> MIC->Host Memory) Is it possible?
In case you don't know, this question was posted and it receives some comments at Intel Many Integrated Core Architecture Forum https://software.intel.com/en-us/forums/topic/540368

Reserve GPU for one exclusive OpenCL host programme

Is there a possibility to exclusively reserve the GPU for an OpenCL host programme?
No other process shall have access to this device via OpenCL or OpenGL.
Background is that my software calculates real time data on the GPU and therefore it's not good for the performance if the GPU is doing other stuff as well.

PCIe Bandwidth on ATI FirePro

I am trying to measure PCIe Bandwidth on ATI FirePro 8750. The amd app sample PCIeBandwidth in the SDK measures the bandwith of transfers from:
Host to device, using clEnqueueReadBuffer().
Device to host, using clEnqueueWriteBuffer().
On my system (windows 7, Intel Core2Duo 32 bit) the output is coming like this:
Selected Platform Vendor : Advanced Micro Devices, Inc.
Device 0 : ATI RV770
Host to device : 0.412435 GB/s
Device to host : 0.792844 GB/s
This particular card has 2 GB DRAM and max clock frequency is 750 Mhz
1- Why is bandwidth different in each direction?
2- Why is the Bandwdith so small?
Also I understand that this communication takes place through DMA, so the Bandwidth may not be affected by CPU.
This paper from Microsoft Research labs give some inkling of why there is asymmetric PCIe data transfer bandwidth between GPU - CPU. The paper describes performance metrics for FPGA - GPU data transfer bandwidth over PCIe. It also includes metrics from CPU - GPU data transfer bandwidth over PCIe.
To quote the relevant section
'it should also be noted that the GPU-CPU transfers themselves also
show some degree of asymmetric behavior. In the case of a GPU to CPU
transfer, where the GPU is initiating bus master writes, the GPU
reaches a maximum of
6.18 GByte/Sec. In the opposite direction from CPU to GPU, the GPU is initiating bus master reads and the resulting bandwidth falls to 5.61
GByte/Sec. In our observations it is typically the case that bus
master writes are more efficient than bus master reads for any PCIe
implementation due to protocol overhead and the relative complexity of
implementation. While a possible solution to this asymmetry would be
to handle the CPU to GPU direction by using CPU initiated bus master
writes, that hardware facility is not available in the PC architecture
in general. '
The answer to the second question on bandwidth could be due units of data transfer size.
See figs 2,3,4 and 5. I have also seen graphs like this at the 1st AMD Fusion Conference. The explanation is that the PCIe transfer of data has overheads due to the protocol and the device latency. The overheads are more significant for small transfer sizes and become less significant for larger sizes.
What levers do you have to control or improve performance?
Getting the right combo of chip/motherboard and GPU is the H/W lever. Chips with the max number of PCIe lanes are better. Using a higher spec PCIe protocol, PCIe 3.0 is better than PCIe 2.0. All components need to support the higher standards.
As a programmer controlling the data transfer size, is a very important lever.
Transfer sizes of 128K - 256K bytes get approx 50% of the max bandwidth. Transfers of 1M - 2M bytes get over 90% of max bandwidth.

What is the difference between microprocessor and microcontroller? [closed]

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One difference is microcontrollers are usually designed to perform a small set of specific functions whereas microprocessors are for huge, general functions.
Anything else??
A microcontroller is a microprocessor (a.k.a. CPU core or cores) with additional peripherals on-chip. The terms come from the 1970s, where a microprocessor (e.g. Motorola 6800 or Intel 8086) would have an address bus, a data bus, and control lines, and a microcontroller (e.g. Motorola 6801 or Intel 8051) would have peripheral I/O pins (serial ports, parallel I/O, timer I/O, etc.) but no external memory bus (you were stuck with what was on the chip).
Additionally, microprocessors executed their programs from external ROM and microcontrollers would use internal masked (as in "programmed at the factory by changing the IC photo mask") ROM. The only practical erasable ROMs were UV-erased EPROMS, electrically erasable PROMS (EEPROMS) were expensive, slow, and not very dense, and "flash" meant the bits of plastic sticking out of the mold seam lines on the chip.
Honestly, the line between them is fading away. Modern microcontrollers such as the Motorola 6812 series have an external memory bus and peripheral I/O pins at the same time, and can be used as either a microprocessor or microcontroller.
From
http://wiki.answers.com/Q/What_is_the_difference_between_a_microprocessor_and_a_microcontroller
A microcontroller is a specialized form of microprocessor that is designed to be self-sufficient and cost-effective, where a microprocessor is typically designed to be general purpose (the kind used in a PC). Microcontrollers are frequently found in automobiles, office machines, toys, and appliances.
The microcontroller is the integration of a number of useful functions into a single IC package. These functions are:
The ability to execute a stored set of instructions to carry out user defined tasks.
The ability to be able to access external memory chips to both read and write data from and to the memory.
Basically, a microcontroller is a device which integrates a number of the components of a microprocessor system onto a single microchip.
So a microcontroller combines onto the same microchip :
The CPU core (microprocessor)
Memory (both ROM and RAM)
Some parallel digital I/O
Also, a microcontroller is part of an embedded system, which is essentially the whole circuit board. Look up "embedded system" on Wikipedia.
The difference is that microcontroller incorporates features of microprocessor(CPU,ALU,Registers)along with the presence of added features like presence of RAM,ROM,I\O ports,counter etc.Here microcontroller control the operation of machine using fixed programme stored in Rom that doesn't change with lifetime.
The other difference is that the micro controllers usually has to handle real time tasks while on the contrary the microprocessors in a computer system may not handle a real time task at all times.
A microcontroller is much more of a complete computer system. A microprocessor is just that -- a processor. A microcontroller will normally include memory (often both RAM and some sort of ROM) as well as peripherals such as serial ports and timers, and (in some case) more specialized hardware. For example, a microcontroller intended for motor control will typically include some PWM ports, while one intended for communication use might include encryption hardware.
In short:
Microprocessor= CPU
Microcontroller= CPU+ peripherals+ memory
This link was useful too.
Micro-controller is a general purpose processor having 40pins. It is used as CPU in computer. It uses memory devices like RAM or ROM externally.
Micro-controller is also a processor designed with memory internally. It may be a computer.
General use
Microprocessor - generally use in computers as a general purpose programmable device.
microcontroller- generally use in Robotic system or a Traffic signal control system.
Ref -Difference between Microprocessor and Microcontroller
In the short word, microprocessor is the one part of microcontroller.

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