dsPIC33EP High Speed PWM module with ADC trigger - microcontroller

Question

I am using the dsPIC33EP (MC) microcontroller via the high speed PWM module to create PWM frequencies between around 30-120Khz. On each PWM interrupt, I need to sample 5 ADC channels (However, I have 9 in total - the other 4 are not critical to be sampled within the ADC interrupt).
The issue I am having, is on the first PWM interrupt, only AN0 is sampled, on the second interrupt, only AN1 is sampled etc... So, currently it takes 9 PWM periods to sample all the ADC channels.
I use MPLAB MCC to initialise the PWM and ADC modules,
Has anyone had this issue before and know how to get around it?
(Note - I change the AD1CON2bits.SMPI to 9 somewhere else in the code so I dont read the CTMU and CTMU Temp channels)
Thanks
/* PWM init */
// PCLKDIV 1;
PTCON2 = 0x00;
// PTPER 4915;
PTPER = 0x1333;
// SEVTCMP 0;
SEVTCMP = 0x00;
// MDC 0;
MDC = 0x00;
// CHOPCLK 0; CHPCLKEN disabled;
CHOP = 0x00;
// PWMKEY 0;
PWMKEY = 0x00;
// MDCS Master; FLTIEN disabled; CAM Edge Aligned; DTC Dead-time function is disabled; TRGIEN enabled; XPRES disabled; ITB Master; IUE disabled; CLIEN disabled; MTBS disabled; DTCP disabled;
PWMCON1 = 0x580;
// MDCS Master; FLTIEN disabled; CAM Edge Aligned; DTC Dead-time function is disabled; TRGIEN disabled; XPRES disabled; ITB Master; IUE disabled; CLIEN disabled; MTBS disabled; DTCP disabled;
PWMCON2 = 0x180;
// MDCS Master; FLTIEN disabled; CAM Edge Aligned; DTC Dead-time function is disabled; TRGIEN disabled; XPRES disabled; ITB Master; IUE disabled; CLIEN disabled; MTBS disabled; DTCP disabled;
PWMCON3 = 0x180;
//FLTDAT PWM1L Low, PWM1H Low; SWAP disabled; OVRENH enabled; PENL enabled; PMOD Redundant Output Mode; OVRENL enabled; OSYNC disabled; POLL enabled; PENH enabled; CLDAT PWM1L Low, PWM1H Low; OVRDAT PWM1L Low, PWM1H Low; POLH disabled;
__builtin_write_PWMSFR(&IOCON1, 0xD700, &PWMKEY);
//FLTDAT PWM2L Low, PWM2H Low; SWAP disabled; OVRENH enabled; PENL enabled; PMOD Redundant Output Mode; OVRENL enabled; OSYNC disabled; POLL enabled; PENH enabled; CLDAT PWM2L Low, PWM2H Low; OVRDAT PWM2L Low, PWM2H Low; POLH disabled;
__builtin_write_PWMSFR(&IOCON2, 0xD700, &PWMKEY);
//FLTDAT PWM3L Low, PWM3H Low; SWAP disabled; OVRENH enabled; PENL enabled; PMOD Redundant Output Mode; OVRENL enabled; OSYNC disabled; POLL enabled; PENH enabled; CLDAT PWM3L Low, PWM3H Low; OVRDAT PWM3L Low, PWM3H Low; POLH disabled;
__builtin_write_PWMSFR(&IOCON3, 0xD700, &PWMKEY);
//FLTPOL disabled; CLPOL disabled; CLSRC FLT1; CLMOD disabled; FLTMOD Fault input is disabled; FLTSRC FLT32;
__builtin_write_PWMSFR(&FCLCON1, 0xFB, &PWMKEY);
//FLTPOL disabled; CLPOL disabled; CLSRC FLT1; CLMOD disabled; FLTMOD Fault input is disabled; FLTSRC FLT32;
__builtin_write_PWMSFR(&FCLCON2, 0xFB, &PWMKEY);
//FLTPOL disabled; CLPOL disabled; CLSRC FLT1; CLMOD disabled; FLTMOD Fault input is disabled; FLTSRC FLT32;
__builtin_write_PWMSFR(&FCLCON3, 0xFB, &PWMKEY);
// PDC1 0;
PDC1 = 0x00;
// PDC2 0;
PDC2 = 0x00;
// PDC3 0;
PDC3 = 0x00;
// PHASE1 0;
PHASE1 = 0x00;
// PHASE2 0;
PHASE2 = 0x00;
// PHASE3 0;
PHASE3 = 0x00;
// DTR1 0;
DTR1 = 0x00;
// DTR2 0;
DTR2 = 0x00;
// DTR3 0;
DTR3 = 0x00;
// ALTDTR1 0;
ALTDTR1 = 0x00;
// ALTDTR2 0;
ALTDTR2 = 0x00;
// ALTDTR3 0;
ALTDTR3 = 0x00;
// TRGCMP 0;
TRIG1 = 0x00;
// TRGCMP 0;
TRIG2 = 0x00;
// TRGCMP 0;
TRIG3 = 0x00;
// TRGDIV 1; TRGSTRT 0;
TRGCON1 = 0x00;
// TRGDIV 1; TRGSTRT 0;
TRGCON2 = 0x00;
// TRGDIV 1; TRGSTRT 0;
TRGCON3 = 0x00;
// BPLL disabled; BPHH disabled; BPLH disabled; BCH disabled; FLTLEBEN disabled; PLR disabled; CLLEBEN disabled; BCL disabled; PLF disabled; PHR disabled; BPHL disabled; PHF disabled;
LEBCON1 = 0x00;
// BPLL disabled; BPHH disabled; BPLH disabled; BCH disabled; FLTLEBEN disabled; PLR disabled; CLLEBEN disabled; BCL disabled; PLF disabled; PHR disabled; BPHL disabled; PHF disabled;
LEBCON2 = 0x00;
// BPLL disabled; BPHH disabled; BPLH disabled; BCH disabled; FLTLEBEN disabled; PLR disabled; CLLEBEN disabled; BCL disabled; PLF disabled; PHR disabled; BPHL disabled; PHF disabled;
LEBCON3 = 0x00;
// LEB 0;
LEBDLY1 = 0x00;
// LEB 0;
LEBDLY2 = 0x00;
// LEB 0;
LEBDLY3 = 0x00;
// CHOPLEN disabled; CHOPHEN disabled; BLANKSEL No state blanking; CHOPSEL No state blanking;
AUXCON1 = 0x00;
// CHOPLEN disabled; CHOPHEN disabled; BLANKSEL No state blanking; CHOPSEL No state blanking;
AUXCON2 = 0x00;
// CHOPLEN disabled; CHOPHEN disabled; BLANKSEL No state blanking; CHOPSEL No state blanking;
AUXCON3 = 0x00;
/* Initialize PWM Generator Interrupt Handler*/
PWM_SetGenerator1InterruptHandler(&PWM_Generator1_CallBack);
IFS5bits.PWM1IF = false;
IEC5bits.PWM1IE = true;
// SYNCOEN disabled; SEIEN disabled; SESTAT disabled; SEVTPS 1; SYNCSRC SYNCI1; SYNCEN disabled; PTSIDL disabled; PTEN disabled; EIPU enabled; SYNCPOL disabled;
PTCON = 0x400;
/* ADC init */
// ASAM enabled; ADDMABM disabled; ADSIDL disabled; DONE disabled; SIMSAM Sequential; FORM Absolute decimal result, unsigned, right-justified; SAMP disabled; SSRC PWM1 Primary Trigger; AD12B 12-bit; ADON enabled; SSRCG enabled;
AD1CON1 = 0x8414;
// CSCNA enabled; VCFG0 AVDD; VCFG1 AVSS; ALTS disabled; BUFM disabled; SMPI Generates interrupt after completion of every 11th sample/conversion operation; CHPS 1 Channel;
AD1CON2 = 0x428;
// SAMC 0; ADRC FOSC/2; ADCS 7;
AD1CON3 = 0x07;
// CH0SA AN0; CH0SB AN0; CH0NB AVSS; CH0NA AVSS;
AD1CHS0 = 0x00;
// CSS26 disabled; CSS25 disabled; CSS24 disabled; CSS31 enabled; CSS30 enabled;
AD1CSSH = 0xC000;
// CSS2 enabled; CSS1 enabled; CSS0 enabled; CSS8 enabled; CSS7 enabled; CSS6 enabled; CSS5 enabled; CSS4 enabled; CSS3 enabled;
AD1CSSL = 0x1FF;
// DMABL Allocates 1 word of buffer to each analog input; ADDMAEN disabled;
AD1CON4 = 0x00;
// CH123SA disabled; CH123SB CH1=OA2/AN0,CH2=AN1,CH3=AN2; CH123NA disabled; CH123NB CH1=VREF-,CH2=VREF-,CH3=VREF-;
AD1CHS123 = 0x00;
//Assign Default Callbacks
ADC1_SetInterruptHandler(&ADC1_CallBack);