alias argument in hierarchy in system verilog - multidimensional-array

Question

Is there way to make this alias statement work , as iob is bidirectional we cannot use assign statement. out of all the available iob pins only specific pins are connected to ddr memory dq bus. the other way we are doing is include iob.svh during instantiation of child module below is the snippets of required and implemented
module top(
input [63:0] ddr_dq
);
localparam NUM_HB = 24;
logic [NUM_HB-1:0][4-1:0][8-1:0] iob;
alias iob[0][0][0] = ddr_dq[0];
phy u_phy (
. iob (iob)
);
endmodule
module phy (
inout [NUM_HB-1:0][4-1:0][8-1:0] iob
);
endmodule
this is the work around implemented, but to get a the location of pin at single glance above alias statement will be useful
module top(
input [63:0] ddr_dq
);
localparam NUM_HB = 24;
logic [NUM_HB-1:0][4-1:0][8-1:0] iob;
//alias iob[0][0][0] = ddr_dq[0];
phy u_phy (
`include iob.svh
);
endmodule
Contents of include iob.svh file is captured below
.iob( {
nc_iob_pin[0]
,ddr_dq[0]
,ddr_dq[1]
,ddr_dq[2]
,ddr_dq[3]
,ddr_dq[4]
,ddr_dq[5]
})

Answer 1

I am not sure which problem you saw. Alias statements only work with 'nets', so declaring iob as just logic, meaning var logic prevents it from being compiled. I did modify your code to make it compilable:
parameter NUM_HB = 24;
module top(
input [63:0] ddr_dq
);
wire logic [NUM_HB-1:0][4-1:0][8-1:0] iob; // 'logic' is optional here
alias iob[0][0][0] = ddr_dq[0];
phy u_phy (
. iob (iob)
);
endmodule
module phy (
inout [NUM_HB-1:0][4-1:0][8-1:0] iob
);
endmodule