I am getting X as clk_out.Example of the frequency divider.
module freq_by2(input clk,rst,output reg clk_out);
always #(posedge clk)
begin
if (rst==1'b1)
begin
clk_out<=0;
end
else
begin
clk_out<=~clk_out;
end
end
endmodule
module freq_by4(input clk,rst,output reg [1:0] clk_out);
freq_by2 f0(.clk(clk),.rst(rst),.clk_out(clk_out[0]));
freq_by2 f1(.clk(clk_out[0]),.rst(rst),.clk_out(clk_out[1]));
endmodule
Are you sure, you are generating a correct, synchronous rst pulse? That is, synchronous to both clk and clk/2, because your f1 instantiation is synchronous to the clk_out output of f0? Otherwise, you are negating the last value of clk_out inside of freq_by2, which is X initially, unless a correct reset was generated.
Related
I have written the following VHDL code with the assumption that it will generate a counter with a synchronous reset! however, when I looked at the elaborated design in Vivado 2020.2, the counter has an ASYNCHRONOUS reset! The process should not get evaluated without seeing the rising/falling edges of the clock! How did the tool infer an asynchronous reset?!
PS. count is defined as an unsigned signal (not std_logic_vector)
Any explanation is greatly appreciated!
process(clk)
begin
if rst='1' then
count <= (others => '0');
elsif rising_edge(clk) then
count <= count + 1;
end if;
end process;
Synthesis tools generally ignore the sensitivity list, and create the logic from design patterns in the code. In your code, the rst branch overrides the clock branch, hence it creates an asynchronous reset. In addition, the reset is not reliant on clk.
To create a synchronous reset, the rst branch should be inside the clock branch as the reset should only occur on a clock edge.
process(clk)
begin
if rising_edge(clk) then
count <= count + 1;
if rst = '1' then
count <= (others => '0');
end if;
end if;
end process;
When designing finite state machines in verilog, I find myself writing code like this a lot to preserve a value in a particular state.
always#(state, a, b) begin
case(state) begin
S1: a = b;
S2: a = a; // preserve a;
endcase
end
This is necessary because if I don’t specify a value for each register in the sensitivity list, the compiler will infer a latch. To me this feels like a code smell, but I’m not experienced enough to know for sure. Is this the best way to preserve a value in verilog?
Preserve state means to create a latch, which is a device that do exactly that.
a=a is a null statement and you should not use it at all.
Do not use sensetivity lists in the always block, they are error prone, use #* instead.
And, for latches, you should use non-blocking assignments.
Your latch case statement should look like the following:
always#(*) begin
case(state) begin
S1: a <= b;
S2: // do nothing about 'a', a will not change.
endcase
end
in general the FSM scheme use in industry uses clocks and looks like the following:
always#(posedge clk) begin
case(state) begin
S1: begin
next_state <= S2;
a <= b;
end
S2: // do nothing about 'a', a will not change.
....
endcase
end
assign state = next_state;
the question in it itself is simple. Is it possible to synthesize an Asynchronous counter in Verilog?
More explanation:
So for example, if I have something like the following code, is it possible to synthesize it?
always #(posedge clk) begin
//rst
if(!rst)begin
enable <=0;
end else begin
enable <= 1;
end
end
//action loop
always #(state) begin
case (state)
0:begin
cnt <= cnt
end
1: begin
cnt <= cnt + 1;
next_state <= 1;
end
default: begin
cnt <= cnt;
end
endcase
end
//state loop
always #(next_state, control, enable) begin
if(enable)begin
if(!control) begin
state <= next_state;
end else begin
state <= 0;
end
end
end
Here the general idea is that the counter will go asynchronously while the input control flag is 0, if it is 1 then the counter will be stopped until the input control flag becomes 0 again.
Note: I know I could try and synthesize the code and see what happens. But before that, I would like to know more and see if people have tried it.
Thanks for reading!!
Your action loop can't be properly synthesized.
What it is doing when state == 1?
Your state loop is synthesizable except but you will produce a latch (to store the value when enable == 0). This block is something that could be done using combinational logic '=' instead of non-blocking assignment '<='.
Verilog case statmenet expression is always true
module test(input clk,
input reset,
output reg[3:0] ledss
);
reg[31:0] dataread;
always #(posedge clk)
begin
case(dataread)
32'b1010101010101010101:ledss='b1010;
endcase
end
endmodule
dont understand why this line executed
32'b1010101010101010101:ledss='b1010;
leds is on same pattern 1010
also after executing this code , leds not on
module test(input clk,
input reset,
output reg[3:0] ledss
);
reg[31:0] dataread;
always #(posedge clk)
begin
if(dataread==32'b1010101010101010101) ledss='b1010;
end
endmodule
but if i execute this,leds is on ,pattern 1010
module test(input clk,
input reset,
output reg[3:0] ledss
);
reg[31:0] dataread;
always #(posedge clk)
begin
case(dataread)
32'b101010101010:
begin
if(dataread==32'b101010101010) ledss='b1010;
end
endcase
end
endmodule
dont understand how case statement works in verilog
I believe you are skipping Verilog simulation and loading your code directly to FPGA.
In simulation. ledss would be X until the patter match is satisfied (both case or if). In the provided code dataread is never assigned so it will be X, therefore in simulation ledss will always be X. In your pastebin links you have dataread driven by a ROM output, so it will have a know output that might match the checking condition.
FPGA synthesizes your RTL and typically goes through some optimization. ledss is not explicitly initialized and has only one possible value if ever assigned. Because of this the optimizer might assume the initial value is don't care, then simplify logic by choosing the initial value to be the same as the only possible value it can be assigned to. Or it might assume the initial value is 0 and keep the logic. For this scenario in general, case tends the follow the former and if tends to follow the latter. Though your code is functionally equivalent, it is uncommon to have a case-statement with only one condition.
I suggest you improve your coding style so your intended behavior is more explicitly understood by the synthesizer and anyone reading your code. Bellow are some suggestions. Remember to assign dataread to a known value. (Note: replaced 32'b1010101010101010101 with the equivalent 32'h0005_5555 for human readability)
always #(posedge clk)
begin
case(dataread)
32'h0005_5555 : ledss <= 4'b1010;
default : ledss <= 4'b1111;
endcase
end
Or equivalent:
always #(posedge clk)
begin
if (dataread == 32'h0005_5555)
ledss <= 4'b1010;
else
ledss <= 4'b1111;
end
If you want ledss to keep the 1010 patter after assignment, then you could do:
always #(posedge clk)
begin
if (reset) begin
ledss <= 4'b1111;
end
case(dataread)
32'h0005_5555 : ledss <= 4'b1010;
endcase
end
Or equivalent:
always #(posedge clk)
begin
if (reset) begin
ledss <= 4'b1111;
end
else if (dataread == 32'h0005_5555) begin
ledss <= 4'b1010;
end
end
I'm trying to write RS232 transmitter module in vhdl for Spartan. According to simulation in Xilinx, it seems to be working fine, but when i try to deploy it on device, it simply doesn't work. I have found out that it might be problem with latches, but somehow I'm not able to pinpoint them. I'm using 50 Mhz clock and the bit rate of transmission is 115200 bs.
This is my vhdl code:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
USE ieee.std_logic_arith.all; -- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity nadajnikRS is
Port ( start : in STD_LOGIC;
reset : in STD_LOGIC;
clk : in STD_LOGIC;
DI : in STD_LOGIC_VECTOR(7 downto 0);
RS_TX : out STD_LOGIC;
busy : out STD_LOGIC);
end nadajnikRS;
architecture Behavioral of transRS is
signal register : STD_LOGIC_VECTOR(8 downto 0) := (others => '1' );
signal counter : INTEGER range 0 to 9 := 0;
signal baud_clk : STD_LOGIC := '0';
signal ready : STD_LOGIC := '0';
type states is (working, free);
signal state: states := free;
signal baud_counter : INTEGER range 0 to 220 := 215;
begin
baud_clock: process (clk)
begin
if rising_edge(clk) then
if (ready = '1') then
if (baud_counter < 218) then
if (baud_counter = 217) then
baud_clk <= '1';
end if;
baud_counter <= baud_counter+1;
else
baud_counter <= 0;
baud_clk <= '0';
end if;
else
baud_counter <= 0;
end if;
end if;
end process baud_clock;
shiftregister : process (baud_clk)
begin
if rising_edge(baud_clk) then
if (state = free) then
RS_TX <= '0';
register (7 downto 0) <= DI;
else
RS_TX <= register(0);
register <= '1' & register(8 downto 1);
end if;
end if;
end process shiftregister;
bitcounter : process (baud_clk)
begin
if rising_edge(baud_clk) then
counter <= counter + 1;
if (counter = 10) then
counter <= 1;
end if;
end if;
end process bitcounter;
shiftstate: process (reset, counter, start)
begin
if (reset = '1') then
ready <= '0';
end if;
if (start = '1') then
ready <= '1';
state <= free;
end if;
if (counter = 1 ) then
state <= working;
elsif (counter = 10) then
state <= free;
end if;
end process;
statemachine : process (state)
begin
case state is
when working => busy <= '1';
when free => busy <= '0' ;
end case;
end process statemachine;
end Behavioral;
During synthesis I get two latch warnings:
Xst:737 - Found 1-bit latch for signal <ready>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
Xst:737 - Found 1-bit latch for signal <state_0>. Latches may be generated from incomplete case or if statements. We do not recommend the use of latches in FPGA/CPLD designs, as they may lead to timing problems.
I tried to eliminate them by adding additional if statements, but nothing seems to work.
I will be grateful for any help,
Ghaad
A process describing a register should have exactly one signal in the sensitivity list, clk (possibly a reset signal as well if you use asynchronous resets), since a register is only sensitive to a single event, namely a clock edge.
Thus your process sensitivity list baud_clock: process (clk,ready) and shiftregister : process (baud_clk, state) already indicate that you have a problem.
When describing a register, always make sure that your if(rising_edge(clk)) surrounds ALL of the described logic. A simple registered process should look like this:
process(clk) begin
-- NO LOGIC HERE
if(rising_edge(clk)) then
if(reset='1') then
-- Synchronous reset logic here.
else
-- All other logic here.
end if;
end if;
-- NO LOGIC HERE
end process;
Look at your 'shiftstate' process, which is responsible for driving 'ready'. How does it drive 'ready' when 'reset' is not 1, and 'start' is not 1? You haven't told it, so it keeps 'ready' unchanged in those cases. That's what 'latch' means: the process needs to remember what 'ready' was before, and keep it the same; your code therefore infers a memory. Make sure that 'ready' is driven in all branches; you can do this easily with a default assignment at the top.
Having said that, your code has multiple other issues. Did someone suggest in another thread that you shouldn't have your rising edge detection inside an if statement? Or was that someone else? Go back and read it again.
Try to fill all the posibilities of if statements so that for every run the program will know which value correspond to a variable. If statement has almost always go with else or elsif options to not produce latches..
A latch can occur when a process is allowed to go from start to finish without the driven outputs being assigned a value. That is if you have any conditional statements in your process and your outputs are driven inside these conditional statements then there a high chance that the outputs may never be driven. To avoid this it is good practice to place a concurrent statement at the beginning of your process to ensure your outputs are being set at least once. This will tell your synthesiser not to create a latch.