Strange behaviour of STM32F407 while writhing to CAN_BTR register - cpu-registers

Question

I defined following user type:
typedef struct
{
union
{
struct
{
uint32_t BRP :10;
uint32_t Reserved_1 :6;
uint32_t TS1 :4;
uint32_t TS2 :3;
uint32_t Reserved_2 :1;
uint32_t SJW :2;
uint32_t Reserved_3 :4;
uint32_t LBKM :1;
uint32_t SILM :1;
};
uint32_t reg;
};
}__attribute__((packed, aligned(1))) _CAN_BTR;
Then created variable:
_CAN_BTR *CAN_BTR = (_CAN_BTR*) &(CAN->BTR);
But when wrighting with following code i get wrong results:
CAN_BTR->TS1 = 9;
CAN_BTR->TS2 = 4;
CAN_BTR->BRP = 6;
CAN_BTR->SJW = 3;
At the end it seems like problem in the wrighting to register, because everithing is fine until
strb r3, [r2, #2]
where r3 hold correct value r2 holds base address of CAN_BTR register and #2 ossfet pionts to third byte of register which holds TS1 value.
After some experiments with asm i figureg out that for some reason
strb r3, [r2, #2]
always modifyes first (offset 0) and third (offset 2) byte of that register. With local varible there is no such problem.
CAN_BTR default value is 0x1230000 and aftar any of following instructons
strb r3, [r2, #0]
strb r3, [r2, #1]
strb r3, [r2, #2]
strb r3, [r2, #3]
it became 0x1290129.
Is there any hardware bug or restriction which i dont know of? I checked out errata for STM32F407 but there nothing about something similar in CAN section.
Thanks in advance for answers.
*UPDATE
There is more about code - disassembly listnig:
79 CAN_BTR->TS1 = 9;
080006da: ldr r2, [r7, #16]
080006dc: ldrb r3, [r2, #2]
080006de: movs r1, #9
080006e0: bfi r3, r1, #0, #4
080006e4: strb r3, [r2, #2]
80 CAN_BTR->TS2 = 4;
080006e6: ldr r2, [r7, #16]
080006e8: ldrb r3, [r2, #2]
080006ea: movs r1, #4
080006ec: bfi r3, r1, #4, #3
080006f0: strb r3, [r2, #2]
81 CAN_BTR->BRP = 6;
080006f2: ldr r3, [r7, #16]
080006f4: movs r2, #0
080006f6: orr.w r2, r2, #6
080006fa: strb r2, [r3, #0]
080006fc: ldrb r2, [r3, #1]
080006fe: bic.w r2, r2, #3
08000702: strb r2, [r3, #1]
82 CAN_BTR->SJW = 3;
08000704: ldr r2, [r7, #16]
08000706: ldrb r3, [r2, #3]
08000708: orr.w r3, r3, #3
0800070c: strb r3, [r2, #3]
Before first line register have default value 0x1230000.
After this line
080006e4: strb r3, [r2, #2]
register value is 0x1290129.
Is there any more code i need to show to illustrate my problem?
*UPDATE 2
Now type defined as:
typedef struct
{
union
{
struct
{
uint32_t BRP :10;
uint32_t :6;
uint32_t TS1 :4;
uint32_t TS2 :3;
uint32_t :1;
uint32_t SJW :2;
uint32_t :4;
uint32_t LBKM :1;
uint32_t SILM :1;
};
uint32_t reg;
};
} _CAN_BTR;
but this lead to identical asm code:
86 CAN_BTR->TS1 = 9;
08000718: ldr r2, [r7, #16]
0800071a: ldrb r3, [r2, #2]
0800071c: movs r1, #9
0800071e: bfi r3, r1, #0, #4
08000722: strb r3, [r2, #2]
*SOULTION
As pionetd out by 0___________ problem was in accessing CAN register as bytes, but reference manual permits only word(32bit) acess. Thanks!

Answer 1

The CAN registers HAVE to be accessed as words. Your code is accessing them as bytes, which is INVALID
Do not introduce pointers as it has a performance penalty.
}__attribute__((packed, aligned(1))) _CAN_BTR; alignment makes no sense. Packing is not needed and will emit very inefficient code and also forces byte access which is invalid!!!
You do not need to name bitfield padding.
typedef struct
{
union
{
struct
{
uint32_t BRP :10;
uint32_t :6;
uint32_t TS1 :4;
uint32_t TS2 :3;
uint32_t :1;
uint32_t SJW :2;
uint32_t :4;
uint32_t LBKM :1;
uint32_t SILM :1;
};
uint32_t reg;
};
}_CAN_BTR;
#define MYCAN_BTR ((volatile _CAN_BTR *)(&CAN -> BTR))
and access bitfields without introducing any overhead.
MYCAN_BTR -> SJW = ....
UPDATE If your compiler generates this code you need to do it different way.
#define MODIFY_CAN_BTR(field,val) do{_CAN_BTR btr = CAN->BTR; btr -> field = val; CAN -> BTR = btr -> reg;}while(0)