Verilog HDL always & case errors - case
I have been working on a FSM which is implemented using Verilog HDL. In the case determining the next state outputs, I have two outputs that need to be assigned. So I tried to use begin and end to put two assignments into a single case. But it still doesn't work. I am not sure if there is some syntax errors which I can't write the code in this way.
module Vending_FSM(
input [2:0] INPUT,
input CLK,
output REL,
output [3:0] AMT
);
// Declaring state and next_state variable
reg[2:0] state, next_state;
// Declaring 6 state parameters
parameter
S0 = 3'b000, // WAIT
S1 = 3'b001, // $5
S2 = 3'b010, // $10
S3 = 3'b011, // $15
S4 = 3'b100, // $20
S5 = 3'b101; // $25
// Determning next state transition
always #(posedge CLK)
begin
state <= next_state; // Positive-edge triggering
end
// Determing next state input
always #(INPUT or state)
begin
case (state)
S0: case (INPUT) // WAIT
3'b000: next_state = S1; // $5
3'b001: next_state = S2; // $10
3'b010: next_state = S4; // $20
3'b011: next_state = S5; // $50
3'b100: next_state = S0; // $100
3'b101: next_state = S0; // PUR
3'b110: next_state = S0; // REF
endcase
S1: case (INPUT) // $5
3'b000: next_state = S2; // $5
3'b001: next_state = S3; // $10
3'b010: next_state = S5; // $20
3'b011: next_state = S5; // $50
3'b100: next_state = S1; // $100
3'b101: next_state = S1; // PUR
3'b110: next_state = S0; // REF
endcase
S2: case (INPUT) // $10
3'b000: next_state = S3; // $5
3'b001: next_state = S4; // $10
3'b010: next_state = S5; // $20
3'b011: next_state = S5; // $50
3'b100: next_state = S2; // $100
3'b101: next_state = S2; // PUR
3'b110: next_state = S0; // REF
endcase
S3: case (INPUT) // $15
3'b000: next_state = S4; // $5
3'b001: next_state = S5; // $10
3'b010: next_state = S5; // $20
3'b011: next_state = S5; // $50
3'b100: next_state = S3; // $100
3'b101: next_state = S3; // PUR
3'b110: next_state = S0; // REF
endcase
S4: case (INPUT) // $20
3'b000: next_state = S5; // $5
3'b001: next_state = S5; // $10
3'b010: next_state = S5; // $20
3'b011: next_state = S5; // $50
3'b100: next_state = S4; // $100
3'b101: next_state = S4; // PUR
3'b110: next_state = S0; // REF
endcase
S5: case (INPUT) // $25
3'b000: next_state = S5; // $5
3'b001: next_state = S5; // $10
3'b010: next_state = S5; // $20
3'b011: next_state = S5; // $50
3'b100: next_state = S5; // $100
3'b101: next_state = S0; // PUR
3'b110: next_state = S0; // REF
endcase
endcase
end
// Determing next state output
always #(INPUT or state)
begin
case (state)
S0: case (INPUT) // WAIT
3'b000: begin
REL = 1'b0; // $5
AMT = 4'b0000;
end
3'b001: begin
REL = 1'b0; // $10
AMT = 4'b0000;
end
3'b010: begin
REL = 1'b0; // $20
AMT = 4'b0000;
end
3'b011: begin
REL = 1'b0; // $50
AMT = 4'b0101;
end
3'b100: begin
REL = 1'b0; // $100
AMT = 4'b1011;
end
3'b101: begin
REL = 1'b0; // PUR
AMT = 4'b0000;
end
3'b110: begin
REL = 1'b0; // REF
AMT = 4'b0000;
end
endcase
S1: case (INPUT) // $5
3'b000: begin
REL = 1'b0; // $5
AMT = 4'b0000;
end
3'b001: begin
REL = 1'b0; // $10
AMT = 4'b0000;
end
3'b010: begin
REL = 1'b0; // $20
AMT = 4'b0000;
end
3'b011: begin
REL = 1'b0; // $50
AMT = 4'b0110;
end
3'b100: begin
REL = 1'b0; // $100
AMT = 4'b1011;
end
3'b101: begin
REL = 1'b0; // PUR
AMT = 4'b0000;
end
3'b110: begin
REL = 1'b0; // REF
AMT = 4'b0001;
end
endcase
S2: case (INPUT) // $10
3'b000: begin
REL = 1'b0; // $5
AMT = 4'b0000;
end
3'b001: begin
REL = 1'b0; // $10
AMT = 4'b0000;
end
3'b010: begin
REL = 1'b0; // $20
AMT = 4'b0001;
end
3'b011: begin
REL = 1'b0; // $50
AMT = 4'b0111;
end
3'b100: begin
REL = 1'b0; // $100
AMT = 4'b1011;
end
3'b101: begin
REL = 1'b0; // PUR
AMT = 4'b0000;
end
3'b110: begin
REL = 1'b0; // REF
AMT = 4'b0010;
end
endcase
S3: case (INPUT) // $15
3'b000: begin
REL = 1'b0; // $5
AMT = 4'b0000;
end
3'b001: begin
REL = 1'b0; // $10
AMT = 4'b0000;
end
3'b010: begin
REL = 1'b0; // $20
AMT = 4'b0010;
end
3'b011: begin
REL = 1'b0; // $50
AMT = 4'b1000;
end
3'b100: begin
REL = 1'b0; // $100
AMT = 4'b1011;
end
3'b101: begin
REL = 1'b0; // PUR
AMT = 4'b0000;
end
3'b110: begin
REL = 1'b0; // REF
AMT = 4'b0011;
end
endcase
S4: case (INPUT) // $20
3'b000: begin
REL = 1'b0; // $5
AMT = 4'b0000;
end
3'b001: begin
REL = 1'b0; // $10
AMT = 4'b0001;
end
3'b010: begin
REL = 1'b0; // $20
AMT = 4'b0011;
end
3'b011: begin
REL = 1'b0; // $50
AMT = 4'b1001;
end
3'b100: begin
REL = 1'b0; // $100
AMT = 4'b1011;
end
3'b101: begin
REL = 1'b0; // PUR
AMT = 4'b0000;
end
3'b110: begin
REL = 1'b0; // REF
AMT = 4'b0100;
end
endcase
S5: case (INPUT) // $25
3'b000: begin
REL = 1'b0; // $5
AMT = 4'b0001;
end
3'b001: begin
REL = 1'b0; // $10
AMT = 4'b0010;
end
3'b010: begin
REL = 1'b0; // $20
AMT = 4'b0100;
end
3'b011: begin
REL = 1'b0; // $50
AMT = 4'b1010;
end
3'b100: begin
REL = 1'b0; // $100
AMT = 4'b1011;
end
3'b101: begin
REL = 1'b1; // PUR
AMT = 4'b0000;
end
3'b110: begin
REL = 1'b0; // REF
AMT = 4'b0101;
end
endcase
endcase
end
endmodule
Thank you in advance.
REL and AMT need to be reg type. As they were inferred wire types which cannot be assigned in always blocks.
module Vending_FSM(
input [2:0] INPUT,
input CLK,
output reg REL,
output reg [3:0] AMT
);
also next_state, REL, and AMT are an inferred latches because it is not explcetly assigned when INPUT equal to 3'b111 and state outside of S0-S5. You can either define all cases in the case statement or/and have a default assignment above the case to a constant of flop. Example:
always #* begin
// default assignment
next_state = state;
// update
case(state)
S0: case (INPUT) // WAIT
//... your existing code, maybe added 3'b111/default case
endcase
// S1..S5: ... your existing code, maybe added case 3'b111/default for INPUT
default : next_state = S0; // in case state not inside S0..S5
endcase
end
always #* begin
// default assignment
REL = 1'b0;
ATM = 4'b0000;
// update
case(state)
//... your existing code
endcase
end
Other notes:
always #(INPUT or state) is technically okay, but is no longer recommenced. Use always #* or always #(*) for auto sensitivity. Specifying the signals for the sensitivity list was required for Verilog-1995. Verilog-2001 added auto sensitivity which reduces the risk of an incomplete sensitivity lists; plus reduces typing.
For cleaner output signals and easier timing analysis, I recommend flopping the outputs. Example:
always #* begin
// default assignment
next_REL = 1'b0;
next_AMT = 4'b0000;
// update
case(state)
//... your existing code but REL and AMT prefixed with next_
endcase
end
always #(posedge clk) begin
state <= next_state;
REL <= next_REL;
AMT <= next_AMT;
end
module Vending_FSM(
input [2:0] INPUT
,input CLK
,output reg REL
,output reg [3:0] AMT
);
// Declaring state and next_state variable
reg[2:0] state, next_state;
reg n_AMT,n_REL;
// Declaring 6 state parameters
parameter
S0 = 3'b000, // WAIT
S1 = 3'b001, // $5
S2 = 3'b010, // $10
S3 = 3'b011, // $15
S4 = 3'b100, // $20
S5 = 3'b101; // $25
always#(posedge clk)
state <= next_state;
// Determing next state input
always#*
casez (state)
S0: casez (INPUT) // WAIT
3'b000: next_state = S1; // $5
3'b001: next_state = S2; // $10
3'b010: next_state = S4; // $20
3'b011: next_state = S5; // $50
3'b10?,
3'b110: next_state = S0; // $100// PUR// REF
endcase
S1: casez (INPUT) // $5
3'b000: next_state = S2; // $5
3'b001: next_state = S3; // $10
3'b01?: next_state = S5; // $20// $50
3'b10?: next_state = S1; // $100// PUR
3'b110: next_state = S0; // REF
endcase
S2: casez (INPUT) // $10
3'b000: next_state = S3; // $5
3'b001: next_state = S4; // $10
3'b01?: next_state = S5; // $20// $50
3'b10?: next_state = S2; // $100// PUR
3'b110: next_state = S0; // REF
endcase
S3: casez (INPUT) // $15
3'b000: next_state = S4; // $5
3'b001, // $10
3'b01?: next_state = S5; // $20// $50
3'b10?: next_state = S3; // $100// PUR
3'b110: next_state = S0; // REF
endcase
S4: casez (INPUT) // $20
3'b0??: next_state = S5; // $5// $10// $20 // $50
3'b10?: next_state = S4; // $100// PUR
3'b110: next_state = S0; // REF
endcase
S5: casez (INPUT) // $25
3'b0??, // $5// $10// $20// $50
3'b100: next_state = S5; // $100
3'b10?: next_state = S0; // PUR// REF
endcase
default: next_state = 'x;
endcase
always #* begin
n_REL = 1'b0;
n_AMT = 4'b0;
case (state)
S0: if(INPUT == 3'b100) n_AMT = 4'b1011;
else if(INPUT == 3'b011) n_AMT = 4'b0101;
S1: if(INPUT == 3'b011) n_AMT = 4'b0110;
else if(INPUT == 3'b100) n_AMT = 4'b1011;
else if(INPUT == 3'b110) n_AMT = 4'b0001;
S2: if(INPUT == 3'b010) n_AMT = 4'b0001;
else if(INPUT == 3'b011) n_AMT = 4'b0111;
else if(INPUT == 3'b100) n_AMT = 4'b1011;
else if(INPUT == 3'b110) n_AMT = 4'b0010;
S3: if(INPUT == 3'b010) n_AMT = 4'b0010;
else if(INPUT == 3'b011) n_AMT = 4'b1000;
else if(INPUT == 3'b100) n_AMT = 4'b1011;
else if(INPUT == 3'b110) n_AMT = 4'b0011;
S4: if(INPUT == 3'b001) n_AMT = 4'b0001;
else if(INPUT == 3'b010) n_AMT = 4'b0011;
else if(INPUT == 3'b011) n_AMT = 4'b1001;
else if(INPUT == 3'b100) n_AMT = 4'b1011;
else if(INPUT == 3'b110) n_AMT = 4'b0100;
S5: if(INPUT == 3'b000) n_AMT = 4'b0001;
else if(INPUT == 3'b001) n_AMT = 4'b0010;
else if(INPUT == 3'b010) n_AMT = 4'b0100;
else if(INPUT == 3'b011) n_AMT = 4'b1010;
else if(INPUT == 3'b100) n_AMT = 4'b1011;
else if(INPUT == 3'b101) n_REL = 1'b1;
else if(INPUT == 3'b110) n_AMT = 4'b0101;
endcase
end
always #(posedge clk) begin
REL <= #1 n_REL;
AMT <= #1 n_AMT;
end
endmodule
Related
pascal scale of notation
I'm doing a procedure that reads numbers character by character.
procedure ReadLongint (var success : boolean; var result : longin);
var
c : char;
res : longint;
pos : integer;
begin
res := 0;
pos := 0;
repeat
read(c);
pos := pos + 1
until (c <> ' ') and (c <> #10);
while (c <> ' ') and (c <> #10) do
begin
if (c < '0') or (c > '9') then
begin
writeln('Unexpected ''', c, ''''' in pos: ', pos);
readln;
success := false;
exit
end;
res := res*10 + ord(c) - ord('0');
read(c);
pos := pos + 1
end;
result := res;
success := true
end;
I'm trying to make it with the ability to select any number systems up to 36.
procedure ReadLongint (var success : boolean; var result : longint; var notation : char);
var
c : char;
res : longint;
pos : integer;
begin
res := 0;
pos := 0;
repeat
read(c);
pos := pos + 1
until (c <> ' ') and (c <> #10);
while (c <> ' ') and (c <> #10) do
begin
if (notation > #48) and (notation < #58) then
begin
res := res*10 + ord(c) - ord('0');
end;
if (notation > #64) and (notation < #91) then
begin
res := res*10 + ord(c) - ord('0');?????????
end;
read(c);
pos := pos + 1;
end;
result := res;
success := true
end;
I'm trying to make it with the ability to select any number systems up to 36.
When choosing from 2 to 10, the reading algorithm is the same res := res*10 + ord(c) - ord('0');
But how to correctly read the number of systems of calculation, from A to Z?
Tell me, please.
Pascal pointers not behaving as expected
For CodinGame I'm building a referee for a card game called War. Rules described here). TL;DR: the persons with the highest drawn card adds both cards to the bottom of his/her card stack.
I've build a linked-list in Pascal to hold the card stacks. But pascal pointers are not behaving as I expect:
For example, I give the program the following input (slightly modified):
9
8C
KD
AH
QH
3D
KD
AH
QH
6D
9
8D
2D
3H
4D
4S
2D
3H
4D
7H
The example output is:
nrCards: 5
Player1: 13 14 12 6
Player2: 2 3 4 7
Player1: 14 12 6
Player2: 3 4 7
Player1: 12 6
Player2: 4 7
Player1: 6
Player2: 7
Player1:
Player2: 6 7
2 5
I.e., the nextNode pointer of the last element is mostly not updated properly...
Code:
program Answer;
{$H+}
uses sysutils, math, strutils;
type
TNode = record
val : Int32;
nextNode : ^TNode;
end;
TNodePtr = ^TNode;
TNodePtrPtr = ^TNodePtr;
var
size1 : Int32;
size2 : Int32;
cards : Array of TNode;
player1first : TNodePtr = nil;
player1last : TNodePtr = nil;
player2first : TNodePtr = nil;
player2last : TNodePtr = nil;
winnerLast : TNodePtrPtr = nil;
i : Int32;
Line: String;
turns : Int32 = 0;
nrCards : Int32 = 1;
cardIt : TNodePtr = nil;
function ParseIn(i : Int32) : String;
begin
ParseIn := ExtractWord(i, Line, [' ']);
end;
function War(pl1it, pl2it : TNodePtr) : Int32;
var
nrCards : Int32 = 5;
i :Int32; // not reuse?
begin
for i := 0 to 3 do begin
pl1it := pl1it^.nextNode;
pl2it := pl2it^.nextNode;
if (pl1it = nil) or (pl2it = nil) then
exit(0);
end;
while (pl1it^.val = pl2it^.val) do begin
nrCards := nrCards + 4;
for i := 0 to 3 do begin
pl1it := pl1it^.nextNode;
pl2it := pl2it^.nextNode;
if (pl1it = nil) or (pl2it = nil) then
exit(0);
end;
end;
if pl1it^.val > pl2it^.val then
// player 1 wins
War := nrCards
else
// player 2 wins
War := -nrCards;
end;
begin
readln(Line);
size1 := StrToInt(ParseIn(1));
Setlength(cards, size1);
for i := 0 to size1-1 do begin
readln(Line);
//writeln(StdErr, Line);
case Line[1] of
'1' : cards[i].val := 10;
'J' : cards[i].val := 11;
'Q' : cards[i].val := 12;
'K' : cards[i].val := 13;
'A' : cards[i].val := 14;
else cards[i].val := Integer(Line[1])-48;
end;
if i = size1-1 then
cards[i].nextNode := nil
else
cards[i].nextNode := #cards[i+1];
end;
readln(Line);
size2 := StrToInt(ParseIn(1));
Setlength(cards, size1+size2);
for i := size1 to size1+size2-1 do begin
readln(Line);
//writeln(StdErr, Line);
case Line[1] of
'1' : cards[i].val := 10;
'J' : cards[i].val := 11;
'Q' : cards[i].val := 12;
'K' : cards[i].val := 13;
'A' : cards[i].val := 14;
else cards[i].val := Integer(Line[1])-48;
end;
if i = size1+size2-1 then
cards[i].nextNode := nil
else
cards[i].nextNode := #cards[i+1];
end;
player1first := #cards[0];
player1last := #cards[size1-1];
player2first := #cards[size1];
player2last := #cards[size1+size2-1];
// now for the game
while (player1first <> nil) and (player2first <> nil) do begin
if player1first^.val <> player2first^.val then begin
if player1first^.val > player2first^.val then begin
// player 1 wins
writeln(StdErr, 'Player1 wins');
winnerLast := #player1last;
end else begin
// player 2 wins
writeln(StdErr, 'Player2 wins');
winnerLast := #player2last;
end;
winnerLast^^.nextNode := player1first;
winnerLast^ := player1first;
player1first := player1first^.nextNode;
winnerLast^^.nextNode := player2first;
winnerLast^ := player2first;
player2first := player2first^.nextNode;
winnerLast^^.nextNode := nil;
end else begin
// war
nrCards := War(player1first, player2first);
writeln(StdErr, 'nrCards: ', nrCards);
if nrCards = 0 then
break;
if nrCards > 0 then begin
writeln(StdErr, 'Player1 wins');
winnerLast := #player1last;
end else begin
writeln(StdErr, 'Player2 wins');
winnerLast := #player2last;
nrCards := -nrCards;
end;
for i := 0 to nrCards-1 do begin
winnerLast^^.nextNode := player1first;
winnerLast^ := player1first;
player1first := player1first^.nextNode;
end;
for i := 0 to nrCards-1 do begin
winnerLast^^.nextNode := player2first;
winnerLast^ := player2first;
player2first := player2first^.nextNode;
end;
winnerLast^^.nextNode := nil;
end;
turns := turns + 1;
write(StdErr, 'Player1: ');
cardIt := player1first;
while cardIt <> nil do begin
write(StdErr, cardIt^.val, ' ');
cardIt := cardIt^.nextNode;
end;
writeln(StdErr, ' ');
write(StdErr, 'Player2: ');
cardIt := player2first;
while cardIt <> nil do begin
write(StdErr, cardIt^.val, ' ');
cardIt := cardIt^.nextNode;
end;
writeln(StdErr, ' ');
end;
// end game
if nrCards = 0 then
// equal
writeln('PAT')
else if player2first = nil then
// player 2 won
writeln('1 ',turns)
else
// player 2 won
writeln('2 ',turns);
flush(StdErr); flush(output); // DO NOT REMOVE
end.
I have a background in C/C++/C#, which could explain my coding style. The same program in C works correctly. IMHO I've literally translated it...
C code:
#define _CRT_SECURE_NO_WARNINGS
#include <stdlib.h>
#include <stdio.h>
#include <string.h>
struct TNode {
int val;
struct TNode* nextNode;
};
int War(struct TNode* pl1It, struct TNode* pl2It) {
int nrCards = 5;
for (int i = 0; i < 4; ++i) {
pl1It = pl1It->nextNode;
pl2It = pl2It->nextNode;
if (pl1It == NULL || pl2It == NULL) {
return 0;
}
}
while (pl1It->val == pl2It->val) {
nrCards += 4;
for (int i = 0; i < 4; ++i) {
pl1It = pl1It->nextNode;
pl2It = pl2It->nextNode;
if (pl1It == NULL || pl2It == NULL) {
return 0;
}
}
}
if (pl1It->val > pl2It->val) {
// player 1 wins
return nrCards;
} else {
// player 2 wins
return -nrCards;
}
}
int main()
{
struct TNode cards[52];
int size1;
scanf("%d", &size1);
for (int i = 0; i < size1; ++i) {
char Line[4];
scanf("%s", Line);
if (Line[0] == '1') cards[i].val = 10;
else if (Line[0] == 'J') cards[i].val = 11;
else if (Line[0] == 'Q') cards[i].val = 12;
else if (Line[0] == 'K') cards[i].val = 13;
else if (Line[0] == 'A') cards[i].val = 14;
else cards[i].val = (int)Line[0] - 48;
if (i == size1 - 1) cards[i].nextNode = NULL;
else cards[i].nextNode = &cards[i + 1];
}
int size2;
scanf("%d", &size2);
for (int i = size1; i < size1 + size2; ++i) {
char Line[4];
scanf("%s", Line);
if (Line[0] == '1') cards[i].val = 10;
else if (Line[0] == 'J') cards[i].val = 11;
else if (Line[0] == 'Q') cards[i].val = 12;
else if (Line[0] == 'K') cards[i].val = 13;
else if (Line[0] == 'A') cards[i].val = 14;
else cards[i].val = (int)Line[0] - 48;
if (i == size1 + size2 - 1) cards[i].nextNode = NULL;
else cards[i].nextNode = &cards[i + 1];
}
struct TNode* player1first = &cards[0];
struct TNode* player1last = &cards[size1 - 1];
struct TNode* player2first = &cards[size1];
struct TNode* player2last = &cards[size1 + size2 - 1];
int nrOfCards = 1; // has to do with check
int turns = 0;
// now for the game
while (player1first != NULL && player2first != NULL) {
if (player1first->val != player2first->val) {
struct TNode** winnerLast = NULL;
if (player1first->val > player2first->val) {
// player 1 wins
fprintf(stderr, "Player 1 wins.\n");
winnerLast = &player1last;
} else {
// player 2 wins
fprintf(stderr, "Player 2 wins.\n");
winnerLast = &player2last;
}
(*winnerLast)->nextNode = player1first;
(*winnerLast) = player1first;
player1first = player1first->nextNode;
(*winnerLast)->nextNode = player2first;
(*winnerLast) = player2first;
player2first = player2first->nextNode;
(*winnerLast)->nextNode = NULL;
} else {
// war
fprintf(stderr, "War: ");
nrOfCards = War(player1first, player2first);
if (nrOfCards == 0) break;
struct TNode** winnerLast;
if (nrOfCards > 0) {
// Player 1 wins
fprintf(stderr, "Player 1 wins.\n");
winnerLast = &player1last;
} else {
// Player 2 wins
fprintf(stderr, "Player 2 wins.\n");
nrOfCards = -nrOfCards;
winnerLast = &player2last;
}
for (int i = 0; i < nrOfCards; ++i) {
(*winnerLast)->nextNode = player1first;
(*winnerLast) = player1first;
player1first = player1first->nextNode;
}
for (int i = 0; i < nrOfCards; ++i) {
(*winnerLast)->nextNode = player2first;
(*winnerLast) = player2first;
player2first = player2first->nextNode;
}
(*winnerLast)->nextNode = NULL;
}
turns = turns + 1;
}
// end game
if (nrOfCards == 0) {
// equal
printf("PAT\n");
} else if (player2first == NULL) {
// player 2 won
printf("1 %d\n", turns);
} else {
// player 2 won
printf("2 %d\n", turns);
}
// Write an action using printf(). DON'T FORGET THE TRAILING \n
// To debug: fprintf(stderr, "Debug messages...\n");
return 0;
}
Can somebody explain why pascal pointers are behaving so differently, or what I am doing wrong?
I found the problem, which I do not fully understand yet. The problem is caused by de use of dynamic array cards. That's also the big difference between the C code and the pascal code. I'm was doing readln(Line); size1 := StrToInt(ParseIn(1)); Setlength(cards, size1); for i := 0 to size1-1 do begin readln(Line); [...] end; readln(Line); size2 := StrToInt(ParseIn(1)); Setlength(cards, size1+size2); for i := size1 to size1+size2-1 do begin That second Setlength seems to have invalidated the last element of my initial array.. It seems player1last^.nextNode and cards[size-1].nextNode were no longer connected. I don't exactly understand what happened underwater... I can only guess that Setlength reallocates the memory and copies the contents thereby invalidating all existing pointers! If this is the case, this was not properly explained in the tutorials I found. I could luckily fix this as there are a maximum of 52 cards, so by choosing a fixed-length array I could fix this. cards : Array[0..51] of TNode; EDIT: OK I found a source giving me the answer Dynamic array - Free Pascal wiki Although writing to elements of dynamic arrays does not create a new instance of the array (no copy-on-write as it exists for Ansistrings) using SetLength on such arrays does create a copy! So if 2 dynamic array variables point to the same array (one has been assigned to the other) they do not do so after using SetLength on one (or both) of them. After the SetLength() call the two variables are distinct arrays whose elements are independent from each other.
the ASCII table symbols are not displayed
The console does not display characters from ASCII from 1 to 31, instead they display question marks in the rectangles. Tell me what to do, please
#include<stdio.h>
#include<stdlib.h>
#include<Windows.h>
#include<conio.h>
#include<time.h>
int main()
{
const int startingMoney = 500;
const int turnCost = 50;
const int doubleBonus = 60;
const int tripleBobus = 100;
int money = startingMoney;
char panel0 = 'X';
char panel1 = 'X';
char panel2 = 'X';
srand(time(NULL));
do
{
system("cls");
printf("\n\n");
printf("\t ######### \n");
printf("\t# BANDITO #\n");
printf("\t###########\n");
printf("\t# #\n");
printf("\t# %c %c %c #\n", panel0, panel1, panel2);
printf("\t# #\n");
printf("\t###########\n");
printf("\n");
printf("\tMoney: %d$\n", money);
_getch();
money = money - turnCost;
panel0 = 3 + (rand() % 4);
panel1 = 3 + (rand() % 4);
panel2 = 3 + (rand() % 4);
if ((panel0 == panel1) && (panel0 == panel2))
{
money = money + tripleBobus;
}
if ((panel0 == panel1) || (panel0 == panel2) || panel1 == panel2)
{
money = money + doubleBonus;
}
} while (money >= turnCost);
return 0;
}
Continuous sequence in VHDL
This is what i am required to do. - Show the following repeating sequence on the onboard LEDs (Leftmost LED is MSB): o 0x00 -> 0x03 -> 0x40 -> 0xE8 -> 0x00 -> … - LED transitions must be visible - Command the sequence to start/pause upon pressing BTN0 - Upon power up the sequence is paused This is what i have so far: entity vhdl_primer is port ( clk, rst_n, btn0: in std_logic; LED: out std_logic_vector (7 downto 0) ); end vhdl_primer; architecture behavior of vhdl_primer is type statetype is (S0, S1, S2, S3); signal currentstate, nextstate: statetype; begin statereg: process(clk, rst) begin if (rst='0') then currentstate <= S0; --initial state elsif rising_edge(clk) then currentstate <= nextstate; end if; end process; comblogic: process(currentstate, btn0) begin LED <= '0'; case currentstate is when S0 => LED <= '0'; -- led off nextstate <= S1; when S1 => if (btn0='1') then nextstate <= S2; else nextstate <= S1; end if; when S2 => LED <= '1'; -- led 0x40 nextstate <= S3; when S3 => LED <= '1'; -- led 0xE8 if (btn0='1') then nextstate <= S0; else nextstate <= S3; end if; when others => end case; end process; end behavior;
output is high before the expected clock edge in the sequence detector in verilog code
Sir, I wrote a verilog code for "1011" sequence detector. But in simulation output is high when it receives "101". ie. it is high one clock cycle before the actual clock edge. Please help me to solve this issue // verilog code module main( input clk, input rst, input x, output y ); reg temp; reg [1:0] present_state; reg [1:0] next_state; parameter [1:0] state_0 = 2'b00; parameter [1:0] state_1 = 2'b01; parameter [1:0] state_2 = 2'b10; parameter [1:0] state_3 = 2'b11; always #(posedge clk or posedge rst) begin if(rst) present_state <= state_0; else present_state <= next_state; end always #(x or present_state) begin case(present_state) state_0 : if( x ) begin next_state = state_1; temp = 1'b0; end else begin next_state = state_0; temp = 1'b0; end state_1 : if( x ) begin next_state = state_1; temp = 1'b0; end else begin next_state = state_2; temp = 1'b0; end state_2 : if( x ) begin next_state = state_3; temp = 1'b0; end else begin next_state = state_0; temp = 1'b0; end state_3 : if( x ) begin next_state = state_1; temp = 1'b1; end else begin next_state = state_2; temp = 1'b0; end default : begin next_state = state_0; temp = 1'b0; end endcase end assign y = temp; endmodule //test bench module tb_main( ); reg clk; reg rst; reg x; wire y; main uut( clk, rst, x, y ); initial begin clk = 1'b0; rst = 1'b1; x =1'b0; #150 rst = 1'b0; end always #50 clk <= ~clk; initial begin #150 x = 1'b0; #100 x = 1'b1; #100 x = 1'b0; #100 x = 1'b1; #200 x = 1'b0; #100 x = 1'b1; #200 rst = 1'b1; #200 $stop; end endmodule also my simulation results is attached to this questionenter image description here
The test bench data should be derived by the clock, as is the case with synchronous design, so at least update the test bench to: initial begin #150; #(posedge clk) x = 1'b0; #100; #(posedge clk) x = 1'b1; #100; #(posedge clk) x = 1'b0; #100; #(posedge clk) x = 1'b1; #200; #(posedge clk) x = 1'b0; #100; #(posedge clk) x = 1'b1; #200; #(posedge clk) rst = 1'b1; #200; #(posedge clk) $stop; end Hopefully that will help you to move along, but there may be other issues for you to find ;-)