Intel FPGA OpenCL: Track down reason for low kernel clock frequency - opencl

Question

I'm implementing an OpenCL design for an Intel Cyclone V FPGA. It is based on a modified Version of the Terasic DE10 Standard OpenCL BSP.
The modification contains a connection to an external AD converter card, connected to the FPGA board, for which a custom VHDL-based Qsys block was implemented, that streams samples at a sample rate of approx 16MHz into an avalon dual-clock FIFO. The output of the FIFO is connected to the kernel clock domain and the Avalon Streaming interface output of the FIFO is exported to the OpenCL kernel as channel as described in the Intel® FPGA SDK for OpenCLTM Standard Edition Programming Guide under topic 5.4.5.4. (Implementing I/O Channels Using the io Channels Attribute).
Currently, the CL kernel simply fetches blocks of contiguous data from the channel and writes it to a global memory buffer. The host then appends the samples to a file. This works stable for AD converter sample rates up to 1MHz, higher sample rates produce lots of dropouts.
Enabling profiling and using the Intel Dynamic Profiler for OpenCL showed the reason, the average kernel clock is as low as 1.3MHz. However, as the an OpenCL system is not compiled through the Quartus IDE but through the command line via aoc, there is not so much information on what was synthesized and what is the reason for such a low clock frequency. So how do I track down the bottleneck of my design with the tools provided by Intel?
Here is a screenshot of the profiling results:
Edit:
Here is the relevant part of the CL kernel and the Qsys Design. Note that the TX path that you find in both is currently not used.
#pragma OPENCL EXTENSION cl_intel_channels: enable
struct TwoChannelSample
{
short2 chanA;
short2 chanB;
};
#define FIFO_DEPTH 32768
channel struct TwoChannelSample rxSamps __attribute__((depth(0))) __attribute__((io("THDB_ADA_rxSamples")));
channel struct TwoChannelSample txSamps __attribute__((depth(0))) __attribute__((io("THDB_ADA_txSamples")));
channel ushort stateChan __attribute__((depth(0))) __attribute__((io("THDB_ADA_state")));
kernel void thdbADARxTxCallback (global const float2* restrict txSamples,
global float2* restrict rxSamples,
global ushort* restrict interfaceState)
{
// get state from interface
*interfaceState = read_channel_intel (stateChan);
// Process sample-wise
for (int i = 0; i < FIFO_DEPTH; ++i)
{
struct TwoChannelSample rxSample = read_channel_intel (rxSamps);
rxSamples[i].x = (float)rxSample.chanA.x;
rxSamples[i].y = (float)rxSample.chanA.y;
rxSamples[i + FIFO_DEPTH].x = (float)rxSample.chanB.x;
rxSamples[i + FIFO_DEPTH].y = (float)rxSample.chanB.y;
}
}