I am confused with the option -lNew in a Makefile.
What is the meaning of -lNEW ?
Do you know where can I get more information?
TARGET = Example
OBJS = main.o user.o
CXXLIBS = -Wall -lNew -D_LARGEFILE_SOURCE -D_FILE_OFFSET_BITS=64
all: $(TARGET)
$(TARGET):$(OBJS)
$(CXX) -o $# $(OBJS) $(LIBS) $(CXXLIBS)
Supposing GCC is your build toolchain, -lNew tells to the linker to add the library called "libNew.so" or "libNew.a" to the list of files to link in the output binary.
Related
Is there a way to make gnatmake tool recompile the Ada's runtime library ("RTS") with the project I'm building file by file? I want to integrate my custom preprocessor that adds some features to ada source code and then compiles it with gcc. I'm passing --GCC=<preprocessor> flag to the gnatmake utility, it figures out dependencies automatically and runs my preprocessor for all of my source files. However I want custom preprocessing to be done on code in the RTS as well, is there any way to do it?
The -a flag tells gnatmake to recompile any RTS files that need to be recompiled.
After a little experiment here it seems that if you copy system.ads (and maybe gnat.ads, interfac.ads .. yes) from the compiler’s adainclude/ directory to your source tree (I think you’ll need to touch it whenever you update your preprocessor), gnatmake may be able do what you want.
$ cp /opt/gcc-4.9.0/lib/gcc/x86_64-apple-darwin13/4.9.0/adainclude/system.ads .
$ gnatmake -a int
gcc -c int.adb
gcc -gnatpg -c -I./ -I- /opt/gcc-4.9.0/lib/gcc/x86_64-apple-darwin13/4.9.0/adainclude/s-stalib.adb
gcc -gnatpg -c -I./ -I- /opt/gcc-4.9.0/lib/gcc/x86_64-apple-darwin13/4.9.0/adainclude/a-except.adb
gcc -gnatpg -c -I./ -I- /opt/gcc-4.9.0/lib/gcc/x86_64-apple-darwin13/4.9.0/adainclude/s-valint.adb
gcc -gnatpg -c system.ads
...
gcc -gnatpg -c -I./ -I- /opt/gcc-4.9.0/lib/gcc/x86_64-apple-darwin13/4.9.0/adainclude/s-conca4.adb
gnatbind -x int.ali
gnatlink int.ali
and, after I realised I hadn’t used -gnata,
$ touch int.adb
$ gnatmake -a -gnata int
gcc -c -gnata int.adb
gcc -gnatpg -c -I./ -gnata -I- /opt/gcc-4.9.0/lib/gcc/x86_64-apple-darwin13/4.9.0/adainclude/s-assert.adb
gnatbind -x int.ali
gnatlink int.ali
(I do not want to use -f here, because it’ll rebuild everything.)
I have an old project for which I'm trying to create a multiple binaries, one for each object in the directory. I cannot for the life of me figure out how to deal with multiple targets in this manner. The following works, but it seems to me I should be able to have one rule to link them all, so to speak,
# compile objects, no problem
%.o: %.c
$(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $#
bin: bin.o
$(CC) -o $# $< ../lib/libfoo.a -lm $(ARCH)
bar: bar.o
$(CC) -o $# $< ../lib/libfoo.a -lm $(ARCH)
One approach that I did get to work is to strip off the suffix from the target name like this, and compile and link in one step, but it feels a little hackish,
%.o: %.c
$(CC) $(CFLAGS) $(CPPFLAGS) $< ../lib/libfoo.a -lm -o $(*F)
Disclaimer: I despise make
UPDATE 1: this is what I ended up with
EXECS = bin bar ...
all: $(EXECS)
%: %.c
#echo "Building $# from $<"
$(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $#.o
$(CC) $(CFLAGS) $(CPPFLAGS) $#.o ../lib/libfoo.a -lm -o $#
The convention is to have something like this at the top of your Makefile:
.PHONY: all
all: bin bar
Thus make all will make bin and bar, and by putting it at the top it's the default target for make without arguments. The .PHONY: documents this as a "metatarget", but also instructs Make to run it even if there happens to be a file called all with a fresh datestamp.
%: %.o
$(CC) -o $# $< ../lib/libfoo.a -lm $(ARCH)
This tells Make how to make them both.
I have a directory with dozens of source and header files. Is there a better or cleaner way than the following %.o target for make to detect changes to header files? When the object is compiled, g++ is invoked with both the .cc and .h files which doesn't seem right, it should find the .h file automatically.
%.o: %.cc %.h
g++ -c $^
OBJECTS=headless-driver.o config.o simplefm2.o emulator.o basis-util.o objective.o weighted-objectives.o motifs.o util.o
learnfun : $(OBJECTS) learnfun.o
g++ $^ -o $#
%.o: %.cc %.h
g++ -c $^
You are specifying $^ which expands to all dependencies. If you just want the first dependency on the Gcc command line, use $< instead.
I have a Makefile that compiles, but I want to change the name of one of the directories from "release" to "objects". This is the original Makefile -
# This makefile compiles ....
INCLUDE = -I/usr/include/X11 -I/usr/local/include -I/usr/local/include/FL/images -I/usr/include/freetype2
CC=g++
CFLAGS=-w -D LINUX -O3 -fpermissive
OBJDIR=release # HERE IS THE DIRECTORY I WANT TO CHANGE
SRCDIR=src
LDFLAGS= -L/usr/X11R6/lib$(LIBSELECT) -lpthread -lfltk -lXext -lXft -lfontconfig -lXinerama -lpthread -ldl -lm -lX11
SOURCES_RAW= robot_driver_agent.cpp robot_driver_position.cpp robot_driver_priorityqueue.cpp main.cpp robot_driver_tree.cpp robot_driver_stack.cpp robot_driver_grid.cpp robot_driver_path.cpp grid_analyzer.cpp tcpserver.cpp tcpclient.cpp servercontrol.cpp clientcontrol.cpp robot.cpp udpserver.cpp udpclient.cpp owncontrol.cpp guiwindow.cpp rs232.cpp
TARGET:= go
TARGETD:= go_d
OBJECTS:=$(SOURCES_RAW:.cpp=.o)
OBJECTS:=$(patsubst %.o, $(OBJDIR)/%.o, $(OBJECTS))
SOURCES:=$(SOURCES_RAW)
SOURCES:=$(patsubst %.cpp, $(SRCDIR)/%.cpp, $(SOURCES))
all: $(TARGET)
$(TARGET): $(OBJECTS)
$(CC) -w -D LINUX $(INCLUDE) $^ -o $# $(LDFLAGS)
release/%.o: src/%.cpp
test -d $(OBJDIR) || mkdir $(OBJDIR)
$(CC) -g -c $< $(CFLAGS) -o $#
debug: $(TARGETD)
$(TARGETD): $(OBJECTS)
$(CC) -w -D LINUX $(INCLUDE) $^ -o $# $(LDFLAGS)
%.o: $(SRCDIR)/%.cpp
$(CC) -c -g $< $(CFLAGS)-o $#
.PHONY : clean
clean:
rm -f $(OBJDIR)/*.o
rm -f $(TARGET) $(TARGETD)
All I do is change the OBJDIR symbol to "objects" so it would just be -
OBJDIR=objects
But when I do that, I get the error -
make: *** No rule to make target `objects/robot_driver_agent.o', needed by `go'.
What am I missing? Is "objects" a word reserved for something in make so I can't use it for directories? Is it something in the make file that I need to change? Honestly, I don't know that much about makefiles so any help at all would be great. Thanks.
You have a rule:
release/%.o: src/%.cpp
...
So that when OBJDIR=release and Make wants to build release/robot_driver_agent.o, it knows just what to do. Then you try OBJDIR=objects, it wants to build objects/robot_driver_agent.o, and it doesn't know how because there's no rule that fits. Try changing the rule to:
$(OBJDIR)/%.o: src/%.cpp
...
I have a Makefile that looks like this
CXX = g++ -O2 -Wall
all: code1 code2
code1: code1.cc utilities.cc
$(CXX) $^ -o $#
code2: code2.cc utilities.cc
$(CXX) $^ -o $#
What I want to do next is to include clean target so that every time
I run make it will automatically delete the existing binary files of code1 and code2 before creating the new ones.
I tried to put these lines at the very end of the makefile, but it doesn't work
clean:
rm -f $#
echo Clean done
What's the right way to do it?
The best thing is probably to create a variable that holds your binaries:
binaries=code1 code2
Then use that in the all-target, to avoid repeating:
all: clean $(binaries)
Now, you can use this with the clean-target, too, and just add some globs to catch object files and stuff:
.PHONY: clean
clean:
rm -f $(binaries) *.o
Note use of the .PHONY to make clean a pseudo-target. This is a GNU make feature, so if you need to be portable to other make implementations, don't use it.
In makefile language $# means "name of the target", so rm -f $# translates to rm -f clean.
You need to specify to rm what exactly you want to delete, like rm -f *.o code1 code2
By the way it is written, clean rule is invoked only if it is explicitly called:
make clean
I think it is better, than make clean every time. If you want to do this by your way, try this:
CXX = g++ -O2 -Wall
all: clean code1 code2
code1: code1.cc utilities.cc
$(CXX) $^ -o $#
code2: code2.cc utilities.cc
$(CXX) $^ -o $#
clean:
rm ...
echo Clean done