Constraints(Time/area..) in Yosys and/or ABC - constraints

Question

I am using the following basic script to synthesize simple adder design
# read design
read_verilog fulladder1.v
hierarchy -check
# high-level synthesis
proc; opt; fsm; opt; memory; opt
# low-level synthesis
techmap; opt
# map to target architecture
abc -g AND,XOR
# split larger signals
splitnets -ports; opt
show
With using
abc -g AND,XOR
command, ABC syhthesis the design just using AND,XOR and NOT (NOT is automatically added) gates.
My questions about this issue are;
1) Is there any way to force YOSYS and/or ABC tools to use just one universal gate (e.g. NAND) for whole design?
&
After using
abc -g AND,XOR
like command.
2) Is there a way to reduce or maximize the number of specified gates(e.g.XOR) by adding constraints (time/area/priority?...) to libraries
or
using special YOSYS and/or ABC commands?
Many thanks in advance...

Answer 1

The "cost" of built-in cell types is hardcoded in kernel/cost.h.
When mapping to a custom cell library you can specify the cost (area) in your liberty file. See examples/cmos/cmos_cells.lib for an example.
ABC needs a NOT gate in the cell library. But you can always map to a cell library of e.g. NAND and NOT and then use the techmap command to replace all instances of NOT with a NAND with both inputs driven by the same signal (or one input driven by constant 1, whatever you prefer).
Edit: Mapping NOT to NAND with techmap is easy. Simply create a file named not2nand.v with the following contents:
module \$_NOT_ (input A, output Y);
\$_NAND_ _TECHMAP_REPLACE_ (.A(A), .B(A), .Y(Y));
endmodule
Then you can map NOT gates to NANDs using techmap -map not2nand.v.