VHDL Synthesis, can`t make code be synthesizable - encryption

Question

I have some code on VHDL language, this code male some encryption/decryption operation. Help me please make this code be synthesizable because Xilinx IDE told me that
line 82: Operator must have constant modulo operand.
This is my code. Maybe you have some wish for me how I can refactor it.
library ieee;
use ieee.std_logic_1164.all;
use ieee.STD_LOGIC_TEXTIO.all;
use ieee.STD_LOGIC_UNSIGNED.all;
use ieee.STD_LOGIC_SIGNED.all;
use ieee.NUMERIC_STD.all;
use ieee.NUMERIC_BIT.all;
use ieee.std_logic_arith.all;
use ieee.MATH_REAL.all;
use ieee.MATH_COMPLEX.all;
entity comp is
port(
clk : in STD_LOGIC;
word : in INTEGER;
n : inout INTEGER;
v1 : out INTEGER;
v2 : out INTEGER;
v3 : out INTEGER;
v4 : out INTEGER;
v5 : out INTEGER;
v6 : out INTEGER;
v7 : out INTEGER;
v8 : out INTEGER
);
end comp;
architecture arch of comp is
---- Signal declarations used on the diagram ----
signal g1 : INTEGER := 1;
signal g2 : INTEGER := 1;
signal g3 : INTEGER := 1;
signal k1 : INTEGER := 0;
signal k2 : INTEGER := 0;
signal k3 : INTEGER := 0;
signal m1 : INTEGER;
signal m2 : INTEGER;
signal m3 : INTEGER;
---signal n : INTEGER;
signal p1 : INTEGER;
signal p1_g1 : INTEGER;
signal p2 : INTEGER;
signal p2_g2 : INTEGER;
signal p3 : INTEGER;
signal p3_g3 : INTEGER;
signal sqrt1 : INTEGER;
signal sqrt2 : INTEGER;
signal sqrt3 : INTEGER;
signal w : INTEGER;
---signal word : INTEGER;
begin
---- Processes ----
read : process (clk)
begin
if clk'event and clk = '1' then
n <= p1 * p2 * p3;
w <= word * word MOD n;
sqrt1 <= w MOD p1;
sqrt2 <= w MOD p2;
sqrt3 <= w MOD p3;
if k1*k1 MOD p1 /= sqrt1 then
k1 <= k1 + 1;
else
g1 <= k1;
end if;
if k2*k2 MOD p2 /= sqrt2 then
k2 <= k2 + 1;
else
g2 <= k2;
end if;
if k3*k3 MOD p3 /= sqrt3 then
k3 <= k3 + 1;
else
g3 <= k3;
end if;
p1_g1 <= p1 - g1;
p2_g2 <= p2 - g2;
p3_g3 <= p3 - g3;
m1 <= n / p1;
m2 <= n / p2;
m3 <= n / p3;
v1 <= (-m1 * g1 + m2 * g2 + m3 * g3) MOD n;
v2 <= (-m1 * g1 + m2 * g2 + m3 * p3_g3) MOD n;
v3 <= (-m1 * g1 + m2 * p2_g2 + m3 * g3) MOD n;
v4 <= (-m1 * g1 + m2 * p2_g2 + m3 * p3_g3) MOD n;
v5 <= (-m1 * p1_g1 + m2 * g2 + m3 * g3) MOD n;
v6 <= (-m1 * p1_g1 + m2 * g2 + m3 * p3_g3) MOD n;
v7 <= (-m1 * p1_g1 + m2 * p2_g2 + m3 * g3) MOD n;
v8 <= (-m1 * p1_g1 + m2 * p2_g2 + m3 * p3_g3) MOD n;
end if;
end process;
end arch;

Answer 1

In VHDL/verilog MOD ,REM and DIVISION operators are not synthesizable. Division is only possible when the second operand is a power of 2.
even if you want to traverse your code using a loop to find the remainder you need to put a constant in the condition segment to get your code synthesized.