I am abit new to VHDL and trying to write a code that count frequency of counter clock.I had counter clock was driven by 12MHz. But I used clock register to slow it down to 45.7Hz by choosing clock register (17).
So what I did was created a reference clock at the same time at higher frequency to accuracy reasons. I used clock register (14) in this case which is 366Hz. I used a reference clock counter as well to say when it is 366HZ which is 1 second. and when it is 137 then reset everything.
I'm not too sure what was wrong with the code in this situation. Any advice would be greatly appreciated.
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
--library MACHXO3;
--use MACHXO3.all;
entity testCC2510 is
port(clkin: in std_logic;
reset: in std_logic;
SW4: in std_logic;
LED: out std_logic_vector(7 downto 0);
com: out std_logic;
D2_out: out std_logic_vector(6 downto 0);
D1_out: out std_logic_vector(6 downto 0);
D0_out: out std_logic_vector(6 downto 0);
DP1_out: out std_logic;
DP2_out: out std_logic;
LED_out: out std_logic_vector(7 downto 0));
-- define the pin connections
attribute loc:string;
attribute loc of clkin: signal is "C8";
attribute loc of D0_out: signal is "R13,T14,T12,R11,T11,M11,N10";
attribute loc of D1_out: signal is "R10,P10,T10,R9,T9,N9,M8";
attribute loc of D2_out: signal is "M6,L8,T8,P8,R7,R8,T7";
attribute loc of com: signal is "P7";
attribute loc of reset: signal is "D2";--was K1
attribute loc of SW4: signal is "N1";
attribute loc of DP1_out: signal is "P9";
attribute loc of DP2_out: signal is "P11";
attribute loc of LED_out: signal is "F3,D3,G3,C2,F5,E3,B1,C1";
end;
architecture arch_testCC2510 of testCC2510 is
component SevenSeg
port(LEDin: in integer;
SevSegout: out std_logic_vector);
end component;
signal ref_clk : std_logic; --reference clk
signal ref_counter: integer range 0 to 183; -- reference counter
signal display_0: integer range 0 to 9;
signal display_1: integer range 0 to 9;
signal clkreg : std_logic_vector(31 downto 0);
signal c_clk: std_logic;
signal dig2: std_logic_vector(6 downto 0):="1111111";
signal dig1: std_logic_vector(6 downto 0);
signal dig0: std_logic_vector(6 downto 0);
signal DP1: std_logic:='1';
signal DP2: std_logic:='1';
signal count0: integer range 0 to 9;
signal count1: integer range 0 to 9;
signal oscpin: std_logic;
begin
clk1:process(clkin)
begin
if (clkin'event and clkin = '1') then
clkreg <= clkreg+X"00000001";
end if;
ref_clk <= clkreg (14);
c_clk <= clkreg(17);
oscpin <= clkreg(15);
end process clk1;
--LCD modulation to avoid damage to LCD screen
lcdmod:process(oscpin)
begin
if (oscpin='1') then
D2_out<=dig2;
D1_out<=dig1;
D0_out<=dig0;
DP1_out<=DP1;
DP2_out<=DP2;
else
D2_out<= not dig2;
D1_out<= not dig1;
D0_out<= not dig0;
DP1_out<= not DP1;
DP2_out<= not DP2;
end if;
com<=oscpin;
end process;
DD0:SevenSeg port map(display_0,dig0);
DD1:SevenSeg port map(display_1,dig1);
p_counter: process
begin
wait until rising_edge(c_clk);
if (SW4='1') then
if (((count1=9) and (count0=9)) or reset='0') then
count1<=0;
count0<=0;
elsif(count0=9) then
count1<=count1+1;
count0<=0;
else
count0<=count0+1;
end if;
end if;
--
end process p_counter;
Ref_cnt: process (ref_clk)
begin
wait until rising_edge (ref_clk);
if (ref_clk = 366) then
display_0 <= count0;
display_1 <= count1;
elseif (ref_clk = 367) then --reset count0 and count1
count0 <= 0;
count1 <= 0;
ref_count <= 0;
else
ref_clk = ref_clk + 1;
end if;
end process Ref_cnt;
LED_out <= "00000000";
end arch_testCC2510;
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity SevenSeg is
port(LEDin: integer range 0 to 9;
SevSegout: out std_logic_vector(6 downto 0));
end;
architecture SevenSeg_arch of SevenSeg is
begin
process(LEDin)
begin
Lab0:case LEDin is
when 0=>SevSegout<="0000001";
when 1=>SevSegout<="1001111";
when 2=>SevSegout<="0010010";
when 3=>SevSegout<="0000110";
when 4=>SevSegout<="1001100";
when 5=>SevSegout<="0100100";
when 6=>SevSegout<="0100000";
when 7=>SevSegout<="0001111";
when 8=>SevSegout<="0000000";
when 9=>SevSegout<="0000100";
end case Lab0;
end process;
end SevenSeg_arch;
Im getting this error on quartus about a syntax error, but Cannot find it:
The program is an generic adder for 8 bits
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY big_adder IS
PORT (a, b: IN STD_LOGIC_VECTOR(31 DOWNTO 0);
cin: IN STD_LOGIC;
sum: OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
cout: OUT STD_LOGIC);
END big_adder;
ARCHITECTURE big_adder OF big_adder IS
SIGNAL carry: STD_LOGIC_VECTOR(8 DOWNTO 0);
COMPONENT carry_lookahead_adder IS
PORT (a, b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
cin: IN STD_LOGIC;
sum: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
cout: OUT STD_LOGIC);
END COMPONENT;
BEGIN
carry(0) <= cin;
gen_adder: FOR i IN 1 TO 8 GENERATE
adder: carry_lookahead_adder PORT MAP(a(4*i–1 DOWNTO 4*i–4), b(4*i–1 DOWNTO 4*i–4), carry(i–1), sum(4*i–1 DOWNTO 4*i–4), carry(i));
END GENERATE;
cout <= carry(8);
END big_adder;big_adder;
The syntax looks valid, except of the last line
END big_adder;big_adder;
You have to remove one of the "big_adder;".
One personal hint: You should train yourself to write clean code from day 1!
I have to solve this problem for my university course:
write in VHDL a circuit which, based on the control signal C, dives
the operations shown in the table and also stores the result in a
register sensitive to the falling edge.
C='0' OUT= A+B; C='1' OUT= A-B. Use only std_logic and std_logic_vector statements. A and B are 8-bit vectors.
Ok, I'll post my soluction and after I'll post my doubts.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity fulladder is
port( a,b,cin: in std_logic;
s,cout: out std_logic);
end fulladder;
architecture FA of fulladder is
signal p,g: std_logic;
begin
p<= a xor b;
g<= a and b;
s<= p xor cin;
cout<= g or (p and cin);
end FA;
entity ripplecarry8bit is
port(a,b:in std_logic_vector(7 downto 0);
cin: in std_logic;
cout: out std_logic;
s: out std_logic_vector(7 downto 0));
end ripplecarry8bit;
architecture RC8 of ripplecarry8bit is
signal c: std_logic_vector(6 downto 0);
component fulladder is
port(a,b,cin: in std_logic;
cout,s: out std_logic);
end component;
begin
fa0: fulladder port map(a(0),b(0),cin,c(0),s(0));
fa1: fulladder port map(a(1),b(1),c(0),c(1),s(1));
fa2: fulladder port map(a(2),b(2),c(1),c(2),s(2));
fa3: fulladder port map(a(3),b(3),c(2),c(3),s(3));
fa4: fulladder port map(a(4),b(4),c(3),c(4),s(4));
fa5: fulladder port map(a(5),b(5),c(4),c(5),s(5));
fa6: fulladder port map(a(6),b(6),c(5),c(6),s(6));
fa7: fulladder port map(a(7),b(7),c(6),cout,s(7));
end RC8;
entity ripplecarry9bit is
port(a,b:in std_logic_vector(8 downto 0);
cin: in std_logic;
cout: out std_logic;
s: out std_logic_vector(8 downto 0));
end ripplecarry9bit;
architecture RC9 of ripplecarry9bit is
signal c: std_logic_vector(7 downto 0);
component fulladder is
port(a,b,cin: in std_logic;
cout,s: out std_logic);
end component;
begin
fa0: fulladder port map(a(0),b(0),cin,c(0),s(0));
fa1: fulladder port map(a(1),b(1),c(0),c(1),s(1));
fa2: fulladder port map(a(2),b(2),c(1),c(2),s(2));
fa3: fulladder port map(a(3),b(3),c(2),c(3),s(3));
fa4: fulladder port map(a(4),b(4),c(3),c(4),s(4));
fa5: fulladder port map(a(5),b(5),c(4),c(5),s(5));
fa6: fulladder port map(a(6),b(6),c(5),c(6),s(6));
fa7: fulladder port map(a(7),b(7),c(6),c(7),s(7));
fa8: fulladder port map(a(8),b(8),c(7),cout,s(8));
end RC9;
entity complement is
port(a: in std_logic_vector(7 downto 0);
b: out std_logic_vector(8 downto 0));
end complement;
architecture COM of complement is
signal temp: std_logic_vector(7 downto 0);
component ripplecarry8bit is
port(a,b: std_logic_vector(7 downto 0);
cin: in bit;
cout: out bit;
s: out bit_vector(7 downto 0));
end component;
begin
temp<= not a;
rc: ripplecarry8bit port map(temp, "00000001", '0', b(8), b(7 downto 0));
end COM;
entity register is
port( d: in std_logic_vector(9 downto 0);
clk, clear: in std_logic;
q: out std_logic_vector(9 downto 0));
end register;
architecture R of register is
begin
process(clk, clear)
begin
if clear='1' then
q<="000000000";
elsif clock'event and clock='0' then
q<=d;
end if;
end process;
end R;
entity exam is
port( A,B: in std_logic_vector(7 downto 0);
clk, clear: in std_logic;
OUT: out std_logic_vector(9 downto 0));
end exam;
architecture E of exam is
signal compB, AA, BB: std_logic_vector(8 downto 0);
signal SUM, SUB, O: std_logic_vector(9 downto 0);
component complement is
port(a: in std_logic_vector(7 downto 0);
b: out std_logic_vector(8 downto 0));
end component;
component ripplecarry9bit is
port(a,b:in std_logic_vector(8 downto 0);
cin: in std_logic;
cout: out std_logic;
s: out std_logic_vector(8 downto 0));
end component;
component register is
port( d: in std_logic_vector(9 downto 0);
clk, clear: in std_logic;
q: out std_logic_vector(9 downto 0));
end component;
COM: complement port map(B, compB);
AA<= A(7) & A; --I'm extending A to 9-bit vector
BB<= B(7) & B; --I'm extending B to 9-bit vector
RCSUM: ripplecarry9bit port map (AA, BB, '0', SUM(9), SUM(8 downto 0));
RCSUB: ripplecarry9bit port map (AA, compB, '0', SUB(9),SUB(8 downto 0));
O<= SUM when C='1',
SUB when C='0';
R: register port map(O, clk, clear, OUT);
end E;
I'll explain my doubts.
1) I don't know if RCSUB: ripplecarry9bit port map (AA, compB, '0', SUB(9),SUB(8 downto 0)); is legit cause compA has the left bit as a sign and I don't know if for AA it's the same (it's not explicated in exercise structure).
2) 9-bit vector + 9-bit vector could give as output a 10-bit vector(I use this case as output) but could give as output a 9-bit vector, how can I manage this case in VHDL language?
I'm translating a VHDL code to Verilog but I have a question in VHDL:
What is the use of the concatenation with the empty string in these lines?
Xp_m5b0 <= XX_m5(23 downto 0) & "";
Yp_m5b0 <= YY_m5(23 downto 0) & "";
It is said that it changes the type, but the types here are the same (std_logic_vector).
Here are the lines that showed the type:
entity IntMultiplier_LogicOnly_24_24_48_unsigned_F400_uid4 is
port ( clk, rst : in std_logic;
X : in std_logic_vector(23 downto 0);
Y : in std_logic_vector(23 downto 0);
R : out std_logic_vector(47 downto 0) );
end entity;
signal XX_m5 : std_logic_vector(23 downto 0);
signal YY_m5 : std_logic_vector(23 downto 0);
signal Xp_m5b0 : std_logic_vector(23 downto 0);
signal Yp_m5b0 : std_logic_vector(23 downto 0);
XX_m5 <= X ;
YY_m5 <= Y ;
In verilog after translation, this concatenation gives a compilation error:
assign Xp_m5b0 = {XX_m5[23:0], 0'b };
assign Yp_m5b0 = {YY_m5[23:0], 0'b };
So does it have a difference in the meaning if I removed it and made it like this:
assign Xp_m5b0 = XX_m5[23:0];
assign Yp_m5b0 = YY_m5[23:0];
"" is not an empty string, but an empty array. I haven't seen it used in this context, but it can be used to convert a literal to an array. I.e. consider the next code:
entity e is end entity;
library ieee;
architecture a of e is
use ieee.std_logic_1164.all;
signal a : std_logic_vector(0 downto 0);
signal b : std_logic;
begin
-- a <= b; -- fails
a <= b&""; -- works
end architecture;
But since XX_m5(23 downto 0) is already an array (slice), it should not be required here...
I am writing a project is systemC and i have a couple of sc_in<bool> and sc_out<bool> to communicate between my modules. When I synthesize the project, in the vhdl code produced each sc_in and sc_out creates a block of signals like this:
valid_in_address0 : OUT STD_LOGIC_VECTOR (2 downto 0);
valid_in_ce0 : OUT STD_LOGIC;
valid_in_we0 : OUT STD_LOGIC;
valid_in_d0 : OUT STD_LOGIC_VECTOR (0 downto 0);
valid_in_q0 : IN STD_LOGIC_VECTOR (0 downto 0);
valid_in_address1 : OUT STD_LOGIC_VECTOR (2 downto 0);
valid_in_ce1 : OUT STD_LOGIC;
valid_in_we1 : OUT STD_LOGIC;
valid_in_d1 : OUT STD_LOGIC_VECTOR (0 downto 0);
valid_in_q1 : IN STD_LOGIC_VECTOR (0 downto 0);
This is way too complicated as for my hardware design as I only want to have 1 signal declared like this:
valid_in : IN STD_LOGIC
Declaring a variable as sc_bit, I had no problem with the generated VHDL but after I tried using sc_in<sc_bit> instead of sc_in<bool> in my signals to communicate between modules the project does not compile anymore. If I assign values like this:
sc_bit asdf = 0;
I get the following message:
../../../../source.cpp:67:16: error: conversion from 'int' to
non-scalar type 'sc_dt::sc_bit' requested
If I assign values like this:
sc_bit asdf = '0';
I get the following message:
../../../../source.cpp:68:14: error: no match for 'operator=' in
'((source*)this)->source::asdf = '0''
Is there any other way to declare I/O signals in SystemC so that after synthesis I will only have 1 std_logic signal in VHDL?
The SC_MODULE for the source in the testbench goes like this
header file:
# ifndef SOURCE_H
# define SOURCE_H
# include "systemc.h"
using namespace std;
SC_MODULE(source) {
sc_in_clk clk;
sc_out<sc_bit > valid_out;
void do_cycle();
SC_CTOR(source) {
{
//irrelevant initializations
}
SC_THREAD(do_cycle) {
//i know sc_thread is unsynthesizable but source is testbench
//and i need the signal to be sc_out<sc_bit> to give it as
//input in my top function to be synthesized
}
};
#endif //SOURCE_H
cpp file:
#include "source.h"
void source::do_cycle() {
valid_out = '0';
while(true) {
wait(clk.posedge_event());
//do different kind of stuff
}
}