I am new to vhdl and am attempting to write vhdl odd parity checker using Case within a process. When I compile there are no errors, but the output vector waveform for the output is flat for some reason. What am I doing wrong? Can someone assist me with this or point me in the right direction? Is there another way of doing this?
Here is my code:
library ieee;
use ieee.std_logic_1164.all;
entity test3 is
port (
w, x, y, z : in std_logic;
g1_562 : out std_logic);
end entity test3;
architecture sig of test3 is
signal inputs : std_logic_vector(3 downto 0);
signal outputs: std_logic;
begin
process(inputs) is
begin
case inputs is
when "0000" => outputs <= '1';
when "0011" => outputs <= '1';
when "0101" => outputs <= '1';
when "0110" => outputs <= '1';
when "1001" => outputs <= '1';
when "1010" => outputs <= '1';
when "1100" => outputs <= '1';
when "1111" => outputs <= '1';
when others => outputs <= '0';
g1_562 <= outputs;
end case;
end process;
end architecture sig;
The output is: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
but should be: 1 0 0 1 0 1 1 0 0 1 1 0 1 0 0 1
Thank you
Your signal inputs are never assigned to anything. You need a line outside the process where you concatenate the inputs w, x, y and z. Such as:
inputs <= w & x & y & z;
You should also move g1_562 <= outputs; outside the process.
Related
/*#
requires 0 <= lb < N_LOG_BLOCKS && 0 <= lp < N_PAGE ;
requires ( 1 <= h_clean_counter + l_clean_counter <= N_PHY_BLOCKS );
requires 0 <= h_act_block_index_p < N_PHY_BLOCKS && 0 <= h_act_page_p < N_PAGE;
requires 0 <= l_act_block_index_p < N_PHY_BLOCKS && 0 <= l_act_page_p < N_PAGE;
requires 0 <= l_to_p[lb][lp] < N_PHY_BLOCKS * N_PAGE || l_to_p[lb][lp] == -1;
requires -2147483648 <= d <= 2147283647 ;
requires 0 <= chance_index_p < LRU_SIZE;
requires 0 <= index_2_physical[h_act_block_index_p] < N_PHY_BLOCKS ;
requires \forall integer i; 0 <= i < N_PHY_BLOCKS ==> 0 <= index_2_physical[i] < N_PHY_BLOCKS;
requires 0 <= l_array_counter < N_PHY_BLOCKS/2;
requires l_clean_counter == low_array_counter;
requires h_clean_counter == high_array_counter;
...
*/
My code has tons of variables with some intended bound. As a result, I need to put all these bound constraints in all "requires" and "ensures" regions of all functions. I wonder whether there is a smarter way for me to specify the variable bound, preferably in a global manner.
If these bounds are indeed the same for all functions and you have global variables or the formals are consistently named across all functions, I'd say that this is something MetAcsl can do for you, with something like (for your first requires)
/*# meta \prop,
\name(lb_bounds),
\context(\precond),
\targets(\ALL),
0 <= lb < N_LOG_BLOCKS;
*/
[NB: I haven't tried to type-check it, it may contain typos]
Basically, this tells MetAcsl to insert a pre-condition (because of the \precond context) to \ALL functions saying 0<= lb < N_LOG_BLOCKS.
You can find more information about the annotations that can be generated by MetAcsl on its gitlab repository.
I just started to learn some ada code and would create my very own primes calculator.
To procress, I use one of most known method, which is :
"each primes is a result of 6 * x -+ 1 "
So this is my code :
with Ada.Text_IO, Ada.Integer_Text_IO ;
use Ada.Text_IO, Ada.Integer_Text_IO ;
procedure main is
count_prime : Integer := 0 ;
counter : Integer := 1 ;
wanted : Integer ;
iteration : Integer := 0 ;
testing : Integer := 0 ;
is_prime : Boolean ;
answer : Character ;
begin
loop
Put("Prime calculator") ;
New_line(2) ;
Put("Put 'p' to process") ;
New_Line(1);
Put("Put 'q' to quit") ;
New_Line(2) ;
Put(">> ") ;
Get(answer) ;
if answer = 'p' then
Put("Enter wanted primes :");
Get(wanted) ;
Skip_line ;
if wanted > 0 then
Put("2");
New_Line(1);
if wanted > 1 then
Put("3");
New_Line(1);
end if ;
if wanted > 2 then
count_prime := 2;
loop
if counter = 1 then
counter := 0 ;
iteration := iteration + 1 ;
testing := ( 6 * iteration ) - 1 ;
else
counter := 1 ;
testing := ( 6 * iteration ) + 1 ;
end if ;
is_prime := True ;
for i in 2..(testing-1) loop
if (testing rem i = 0) then
is_prime := False ;
end if ;
end loop;
if is_prime = True then
Put(testing);
New_Line(1);
count_prime := count_prime + 1 ;
end if ;
exit when count_prime = wanted;
end loop ;
end if;
Put("Ended") ;
else
Put("It's can't be a negative number");
end if ;
end if ;
New_Line(3);
exit when answer = 'q' ;
end loop ;
end main ;
I really know this is a basic, I mean ouh, extremely basic program. But I would just solve the problem I've asked :
with 'p' and 2 :
2
3
with 'p' and '7'
2
3
5
7
11
13
17
with 'p' and 1200
2
3
19
23
29
31
37
41
....
Where are gone all primes between 3 and 19 ?
You keep running the calculation in a cycle, but do not reset it's initial state. The loop that performs the calculation continues using values of iteration, counter and a few other variables from the previous run.
Either decompose the loop into a separate procedure, or at least surround it with declare block, e.g.:
declare
count_prime : Integer := 2;
counter : Integer := 1;
iteration : Integer := 0;
testing : Integer := 0;
is_prime : Boolean;
begin
loop
…
end loop;
end;
However, I'd strongly recommend decomposing into a separate procedure.
if wanted > 2 then
count_prime := 2;
-- you probably want to reset iteration here...
iteration := 0;
loop
if counter = 1 then
I've got a 2x2 array of 4-bit std_logic_vector in my VHDL and when I simulate it my tool only gives me a 16 bit std_logic_vector, which bits are which?
More generally: how does VHDL store multidimensional arrays?
From the discussion on this answer it seems that there is no fixed way to store these bits and it's up to the tools you use to provide a correct interface. Mine are apparently a bit wonky.
I did a quick experiment and FOR MY TOOLS it appears the for an array A you get the A(i,j) in the order you specify them. So if you do:
type array_type is array (integer range 0 to 1,integer range 0 to 2) of std_logic_vector(3 downto 0);
you get: A(0,0), A(0,1), A(0,...), A(1,0), A(1,1), A(1,...).
But if you declare your array as:
type array_type is array (integer range 1 downto 0,integer range 2 downto 0) of std_logic_vector(3 downto 0);
(Note we're now using downto) you'll get A(1,2), A(1,1), A(1,0), A(0,2), A(1,1), A(0,0).
I'm making this deduction based on running the following code:
library ieee;
use ieee.std_logic_1164.all;
entity arrays is
port (
x : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0)
);
end entity arrays;
architecture rtl of arrays is
type array_type is array (integer range 0 to 1,integer range 0 to 2) of std_logic_vector(3 downto 0);
signal my_array : array_type;
begin
my_array(0,0) <= "0001";
my_array(0,1) <= "0010";
my_array(0,2) <= "0011";
my_array(1,0) <= "0100";
my_array(1,1) <= "0101";
my_array(1,2) <= "0110";
y <= x;
end architecture rtl;
and getting my_array to be 123456 where each character is a hex number.
Then I switched round the deceleration and got 654321.
So I am trying to use recursion and backtracking to solve a 4x4 sudoku.
When I call SolveSmallSudoku(L);
"Solving now..."
it gives me this "Error, (in SolveSmallSudoku) Matrix index out of range"
But I cannot spot any bug that is related to my matrix, L, indices. It seems like that my program doesn't do my backtracking part properly. I think my findPossibleEntries procedure works fine. It does find all the possible values for that certain cell. Anyone got any hint?
> L := Matrix(4,4,[ [0,4,0,0],[2,0,0,3],[4,0,0,1],[0,0,3,0] ]);
> isFull := proc(L)
local x, y;
for x from 1 to 4 do
for y from 1 to 4 do
if L[x,y]=0 then
return false;
end if;
end do;
end do;
return true;
end proc;
>findPossibleEntries := proc(L, i, j)
local x, y, possible:=[0,0,0,0];
local r:=1, c:=1;
#Checking possible entries in ith row
for y from 1 to 4 do
if not L[i,y] = 0 then
possible[L[i,y]] := 1;
end if;
end do;
#Checking possible entries in jth col
for x from 1 to 4 do
if not L[x,j] = 0 then
possible[L[x,j]] := 1;
end if;
end do;
#Checking possible entries block by block
if i >= 1 and i <= 2 then
r := 1;
elif i >= 3 and i <= 4 then
r := 3;
end if;
if j >= 1 and j <= 2 then
c := 1;
elif j >= 3 and j <= 4 then
c := 3;
end if;
#Using for-loop to find possible entries in the block
for x in range(r, r+1) do
for y in range(c, c+1) do
if not L[x,y] = 0 then
possible[L[x,y]] := 1;
end if;
end do;
end do;
#Now the list, possible, only holds the possible entries
for x from 1 to 4 do
if possible[x] = 0 then
possible[x] := x;
else
possible[x] := 0;
end if;
end do;
return possible;
end proc;
>SolveSmallSudoku := proc(L)
local x, y, i:=0, j:=0, possibleVal:=[0,0,0,0];
if isFull(L) then
print("Solved!");
print(L);
return;
else
print("Solving now...");
for x from 1 to 4 do
for y from 1 to 4 do
if L[x,y] = 0 then
i:=x;
j:=y;
break;
end if
end do;
#Breaks the outer loop as well
if L[x,y] = 0 then
break;
end if
end do;
#Finds all the possibilities for i,j
possibleVal := findPossibleEntries(L,i,j);
#Traverses the list, possibleVal to find the correct entries and finishes the sudoku recursively
for x from 1 to 4 do
if not possibleVal[x] = 0 then
L[i,j]:= possibleVal[x];
SolveSmallSudoku(L);
end if;
end do;
#Backtracking
L[i,j]:= 0;
end if;
end proc;
Get rid of,
#Breaks the outer loop as well
if L[x,y] = 0 then
break;
end if
As you had it originally that outer check was trying to access L[1,5] for your given example L.
Instead, replace the break in the inner loop with,
x:=4; break;
That will cause the outer loop to also complete at the next iteration (which happens to occur right after the inner loop ends or breaks. So you'll get the full break you wanted.
The code then seems to work as you intended, and the solution gets printed for your input example.
I'm trying to do a few mathematical operations on integers in a piece of vhdl code but when i try to compile the tool says "0 definitions of operator "+" match here". Here is what i'm trying to do:
for i in 0 to arr_size - 1 loop
for j in 0 to arr_size - 1 loop
for k in 0 to arr_size - 1 loop
for l in 0 to arr_size - 1 loop
for m in 0 to arr_size - 1 loop
mega_array(i)(j)(k)(l)(m) <= i*(arr_size**4) + j*(arr_size**3) + k*(arr_size**2) + l*(arr_size**1) + m*(arr_size**0);
end loop;
end loop;
end loop;
end loop;
end loop;
The problem was encountered in the line where mega_array is set. Note that this whole block is in a process.
Additionally:
arr_size : integer := 4;
sig_size : integer := 32
type \1-line\ is array (arr_size - 1 downto 0) of unsigned (sig_size - 1 downto 0);
type square is array (arr_size - 1 downto 0) of \1-line\;
type cube is array (arr_size - 1 downto 0) of square;
type hypercube is array (arr_size - 1 downto 0) of cube;
type \5-cube\ is array (arr_size - 1 downto 0) of hypercube;
signal mega_array : \5-cube\;
When reading your older post, the mega_array is an array of 4 levels with at the lowest level an unsigned. In your code in this question I see 5 levels. So at the fifth level you have bit. You can not assign an integer to a std_logic.
Could it be this code is what you want?
for i in 0 to arr_size - 1 loop -- 5-cube
for j in 0 to arr_size - 1 loop -- hypercube
for k in 0 to arr_size - 1 loop -- cube
for l in 0 to arr_size - 1 loop -- square
for m in 0 to arr_size - 1 loop -- 1-line
mega_array(i)(j)(k)(l) <= to_unsigned(i*(arr_size**4) + j*(arr_size**3) + k*(arr_size**2) + l*(arr_size**1), 32);
end loop
end loop;
end loop;
end loop;
end loop;
The to_unsigned functions converts the integer to an unsigned, what is the type of 1-line. The second parameter is the size of the vector to convert the integer into. It must be the same as the size of 1-line.