Pipelining gate 2015 - pipeline

Question

Consider the sequence of machine instructions given below:
MUL R5, R0, R1
DIV R6, R2, R3
ADD R7, R5, R6
SUB R8, R7, R4
In the above sequence, R0 to R8 are general purpose registers. In the instructions shown, the first register stores the result of the operation performed on the second and the third registers. This sequence of instructions is to be executed in a pipelined instruction processor with the following 4 stages:
Instruction Fetch and Decode (IF),
Operand Fetch (OF),
Perform Operation (PO) and
Write back the Result (WB).
The IF, OF and WB stages take 1 clock cycle each for any instruction. The PO stage takes 1 clock cycle for ADD or SUB instruction, 3 clock cycles for MUL instruction and 5 clock cycles for DIV instruction. The pipelined processor uses operand forwarding from the PO stage to the OF stage. The number of clock cycles taken for the execution of the above sequence of instructions is
Since its clearly given that operand forwarding should be used from PO to OF stage, so answer to above should be 15 clock cycles.
But at many places answer is given as 13 clock cycles. 13 answer will come when we use operand forwarding from PO to PO.
My answer:
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
IF OF PO PO PO WB
IF OF PO PO PO PO PO WB
IF OF PO WB
IF OF PO WB
Answer given at many places:
1 2 3 4 5 6 7 8 9 10 11 12 13
IF OF PO PO PO WB
IF OF PO PO PO PO PO WB
IF OF PO WB
IF OF PO WB
can any one tell which answer is correct?

Answer 1

Correct answer is C , 13 clock cycles.
http://geeksquiz.com/gate-gate-cs-2015-set-2-question-54/
http://gateoverflow.in/8218/gate2015-2_44
Operand forwarding takes immediately after the last PO cycle, We do not need to wait one more clock cycle.
so this is the correct sequence
1 2 3 4 5 6 7 8 9 10 11 12 13
IF OF PO PO PO WB
IF OF PO PO PO PO PO WB
IF OF PO WB
IF OF PO WB