I'm learning about computer architecture and I know how a computer works when it executes a program. The thing that makes me confused is when the instruction length is longer than the width of the bus AND the instruction length is NOT the double of the bus width. Let's say we have 12 bit instructions and an 8 bit bus. What does the computer do? Does it:
Analyse the PC
Go to the address of the PC
Fetch 8 bits of the instruction
store 8 bits in instruction register
increase PC by 8 bits (???)
fetch the remaining 4 bits
fill the instruction register (which is 12 bits long?)
Well as you see I'm confused here. I suppose it's not like this, but I need to know in detail how it works and what the PC is after every step.
Would be very grateful for some help! Thanks in advance.
Normally, the smalls amount of memory that can be read or written is 1 byte, i.e. 8 bits. So if the CPU needs 12 bits only, it has to read two 8-bit bytes. From the 16 bits, the required 12 bits are extracted by hardware, and the remaining 4 bits are not used.
Since this is not so memory efficient, the instruction length of a CPU normally is a multiple of 8 bits, e.g. by packing operands directly into the instruction.
So your 7 steps in your example are right except step 6, in which 8 bits are fetched, of which only 4 would be used.
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I am attempting to address 16 bytes on an SRAM chip using 74595 to load memory and then read it later. My issue is the addressing to the memory is 4 bits that I want to control from the Arduino. I would prefer a method to write the decimal value out as binary to the 4 lines at once, but not sure of the best or most efficient method.
So, I have this assignment where I need to design a RISC-32-bit 5 stage pipeline. I must support at least 32 (32-bit) instructions and 32 (32-bit) data values. The memory should be read in 1 clock cycle. Now, for this, I have used a word addressable memory (1 address will contain 32 bits). But, I want to make this byte addressable.
One way of doing this is making the external clock four times slower and then passing these into the other stages of the pipeline. But passing the original clock into the memory part. But, this will make the simulation a bit hectic, like I have to run the clock 20 times (instead of 5).
Another way of doing this will be running a clock (attached to the memory) that will be four times faster than the external clock. So, by the time a single clock cycle passes, memory will be accessed four times so that we would have brought the complete 32-bit. But, circuits for doubling/quadrupling the frequency of a clock seem too complicated.
Are there simpler frequency doubler circuits that can be implemented, or is there any other way to do this?
I am using logisim-evolution to simulate this, and for the memory part, I have used the in-built RAM.
This is the RAM:
The normal way to make a 32-bit byte-addressable memory is to have four 8-bit memory subsystems that are all fed the top N-2 bits of the byte address. When doing a 32-bit load or store, all four memory subsystems will be active. When doing a 16-bit load or store, the second-from-the-bottom address bit will be used control whether to activate the first and second subsystems or the third and fourth. When doing an 8-bit load or store, the bottom address bit will select between the first and second, or between the third and fourth, subsystem.
Why does the stack pointer holds only 8 bit address in 8051 and whereas the program counter holds the 16 bit address?
Every processor can have the width of its pointers deliberately designed. And both PC and SP are pointers, pointing to the instruction to be executed and saved contents on the stack, respectively.
The designers of the 8051 separated instruction memory and data memory. There are more memory sections, but the stack is located in the latter, so this should suffice.
Instruction memory: It has a maximum size of 65536 bytes that can be accesses without further "tricks". To address this range you need 16 bits.
Data memory: It has a maximum size of 256 bytes, even though the standard 8051 has only 128 of them implemented. To address this range you need 8 bits.
Please remember, code and stack are different things!
Code contains all instructions (and if present constants.) It is mostly composed of ROM, but can be RAM.
Stack stores return addresses and saved values. It has to be RAM.
i have encountered some registers in some websites and my textbook. Generally, 16 bit registers are divided into two parts. These two parts with 8 bits are classified L(low) and H(high).
Why is this performed ?
Is it that we work on the 8 bit registers ?
Do these low and high specify an input for utilizing different parts of the register ?
If the cpu you are talking about is from the family of the 8086 processor, yes, it has 16 bits general purpose registers that could be accessed directly, meaning moving the 16 bits at a time, or loading only one byte (8 bits) to either the lower part of the register (the less meaningull bits), or to the higher part of the register (the mos significant bits).
Why is this performed ?
I don't know all the reasons but there must be a mix of trade-offs at the time of designing the cpu. Remember that at that time the predecessors of this cpu were 8 bit cpus which could have caused some back compatibility requirements.
Is it that we work on the 8 bit registers ?
The cpu works with the 16 bits registers but you can address the lower part or the higher part individually.
Do these low and high specify an input for utilizing different parts
of the register ?
Input or output, you could also read their values.
In my work I deal with different micro-controllers, micro-processors and DSP processors. Many of them have 24-bits registers and counters.
I know how to use them, this is not my question.
My question is why do they have 24-bits register! why not make it 32 bit?
and as I know, it is not a problem of size, because the registers are already 32bits, but have maximum of 0xFFFFFF.
Do this provide easier HW implementation? Faster calculations?
Or it is just "hmmm, lets put 24-bits registers to make the job of programmers more hard"?
My guess is that most DSP applications simply don't need 32-bits. Digital audio uses 24-bits fidelity the most. Implementing 32-bits would require more transistors thus would result in higher costs.
Why would 32 bits be easier for the programmer?
Also, you state that the registers have a maximum of 0xFFFFFF, which makes them 24-bits by definition, not 32-bits as you suggest.
There is no particular reason for 8/16/32/64 bits. There are 24 bit DSPs, 18 bit PICs, 36 bit PDP... Each bit costs time, money and power so having enough bits is good enough. No need to over do it. Just look at the original PCs with 20 adress lines, even though the memory pointers could be up to 32 bits.
Tagging onto Tomas' answer, some DSPs have a register mode where overflowing locks the value at the highest state. If the data is 24-bit and it rolls over to the 25th bit, it should lock there, not at the 32-bit rollover.
For audio you would typically want 16 bit output. Since you lose some precision during processing they pick a reasonable size that is somewhat bigger than 16 bit, which happens to be 24 bit.
The reason not to go to full 32 bits is that that would need substantially more hardware, especially for multiplication.