Create one 16-bit vector from two 8-bit vectors - vector

Question

I want to create one 16-bit-vector from two 8-bit-vectors but have errors like below. How to solve it?
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
ENTITY Binary2Gray IS
-- Declarations
port(data : in STD_LOGIC_VECTOR (3 downto 0);
data_out : inout STD_LOGIC_VECTOR (3 downto 0);
data1 : inout std_logic_vector (1 downto 0);
data2 : inout std_logic_vector (1 downto 0);
CLK_I : in std_logic;
y1 : out std_logic_vector (7 downto 0);
y2 : out std_logic_vector (7 downto 0);
op : out std_logic_vector (15 downto 0)
);
END Binary2Gray ;
-----------------------------
ARCHITECTURE rtl OF Binary2Gray IS
signal op : std_logic_vector (15 downto 0);
begin
process(CLK_I)
BEGIN
data_out(3) <=data(3);
data_out(2) <=data(3) xor data (2);
data_out(1) <=data(2) xor data (1);
data_out(0) <=data(1) xor data (0);
label_1: for data_out in 0 to 3 loop
if(data_out = 0 ) then
data1(0) <=data(1) xor data (0);
elsif (data_out = 1 ) then
data1(1) <=data(2) xor data (1);
elsif (data_out = 2 ) then
data2(0) <=data(3) xor data (2);
else
data2(1) <=data(3);
end if;
end loop label_1;
end process;
with data1 select y1 <=
"00110011" when "00",
"00111101" when "01",
"11010011" when "10",
"11011101" when others;
with data2 select y2 <=
"00110011" when "00",
"00111101" when "01",
"11010011" when "10",
"11011101" when others;
op <= y1 & y2 ;
END rtl;
Errors:
# Error: ELAB1_0008: QAM.vhd : (56, 8): Cannot read output : "y1".
# Error: ELAB1_0008: QAM.vhd : (56, 8): Cannot read output : "y2".

Answer 1

In VHDL-2002 (and earlier) it is not allowed to read an output port like y1
and y2, hence the error.
Possible fixes are any of:
declared y1 and y2 as buffer ports
create intermediate signals y1_sig and y2_sig with the values and
assign these to y1, y2, and op
use VHDL-2008 if possible in the tool chain.
Note that op should not be declared as signal when an output port. Note
also that the process does probably not work as expected, since it is not a
clocked process due to missing if rising_edge(CLK_I) then statement, nor a combinatorial
process due to missing data in sensitivity list.