I have the following makefile code:
NAME := test
target1: $(addsuffix .bar,$(NAME))
target2: $(addsuffix .dar,$(NAME))
%.bar: $(INPUT)
touch $#
%.dar: %.bar
touch $#
The I execute this makefile with GNU Make v3.81 like so:
user#node1:/data/user/Tests/oldfile3$ rm test.*
removed `test.bar'
removed `test.txt'
user#node1:/data/user/Tests/oldfile3$ touch test.txt
user#node1:/data/user/Tests/oldfile3$ make target2
touch test.bar
touch test.dar
user#node1:/data/user/Tests/oldfile3$ make target2
make: Nothing to be done for `target2'.
user#node1:/data/user/Tests/oldfile3$ rm test.bar
removed `test.bar'
user#node1:/data/user/Tests/oldfile3$ make target2
make: Nothing to be done for `target2'.
user#node1:/data/user/Tests/oldfile3$
As I expect, intermediate file test.bar is not rebuild after removing it because test.dar is still up-to-date. But when I use GNU Make v3.82:
user#node1:/data/user/Tests/oldfile3$ rm test.*
removed `test.dar'
removed `test.txt'
user#node1:/data/user/Tests/oldfile3$ touch test.txt
user#node1:/data/user/Tests/oldfile3$ mk82 target2
touch test.bar
touch test.dar
user#node1:/data/user/Tests/oldfile3$ mk82 target2
make: Nothing to be done for `target2'.
user#node1:/data/user/Tests/oldfile3$ rm test.bar
removed `test.bar'
user#node1:/data/user/Tests/oldfile3$ mk82 target2
touch test.bar
touch test.dar
user#node1:/data/user/Tests/oldfile3$
Now when I remove test.bar and call make, it will rebuild test.bar and then test.dar. test.txt is still older than test.dar so why remake test.bar which relies on test.txt? This does not happen if I remove target1 like so:
NAME := test
target2: $(addsuffix .dar,$(NAME))
%.bar: $(INPUT)
touch $#
%.dar: %.bar
touch $#
why does it build target1 when I do not specify it anywhere?
Thanks,
Martin
test.bar is not an intermediate file, because it's explicitly mentioned as a prerequisite of target1. It doesn't have to be explicitly mentioned only in the set of targets and prerequisites that make decides to build, it only has to be mentioned explicitly somewhere in the makefile.
After all, it could be that the next time you'll ask to build target1 and then make would have to rebuild test.bar, when it wouldn't have to if it hadn't been deleted.
ETA: I believe the behavior in GNU make 3.81 is a bug.
Related
Say I have a list of source files like this:
SOURCE=aaa.src bbb.src ccc.src
I want to create a rule to build each corresponding target in its own folder, the name of which depends on the soruce file.
Sourcefile ----> Corresponding output file / target
aaa.src -------------------> aaa/aaa.out
bbb.src -------------------> bbb/bbb.out
ccc.src -------------------> ccc/ccc.out
How do I write a rule for this using GNUMake? My best effort was the following Makefile:
.PHONY: all clean
CC=somecompiler
SOURCE := aaa.src bbb.src ccc.src
RTARGS := $(SOURCE:%.src=%.out)
TDIRS := $(addsuffix /,$(basename $(SOURCE)))
TARGS := $(join $(TDIRS), $(RTARGS))
all:$(TARGS)
%.out: $(SOURCE) # Better source specification?
#[ ! -d "$(dir $*)" ] && mkdir "$(dir $*)"
$(CC) "$(patsubst %/,%,$(dir $*)).src" "$#"
clean:
rm -f $(TARGS)
rmdir --ignore-fail-on-non-empty $(TDIRS)
The problem here is, that any one target (i.e. .out file) depends on every source (i.e. .src file), instead of just the one that has the same basename. I could change the commented line to %.out: %.src but than the source file would have to be in the same directory as the output file. I could also compile it something like this:
%.out: %.src
$(CC) "$>" -o "$*/$#"
But then make would always compile every target regardless of whether it already exists or not.
How do I get make to use the appropriate source file only. What is the proper way of specifying dependences for each target separately in a generic rule?
In GNU Make you can specify prerequisites separately from recipes and still have a generic / pattern rule for all .out files:
.PHONY: all clean
all :
SOURCES := aaa.src bbb.src ccc.src
OUTPUTS := $(foreach src,${SOURCES},$(basename ${src})/${src:%.src=%.out})
# Build dependencies in the form of x/x.out : x.src | x
define ESTABLISH_DEPENDENCY =
$(basename ${1})/${1:%.src=%.out} : ${1} | $(basename ${1}) # Also depend on the output directory.
$(basename ${1}) : # Rule to create the output directory.
mkdir $$#
endef
$(foreach src,${SOURCES},$(eval $(call ESTABLISH_DEPENDENCY,${src})))
all : ${OUTPUTS}
# Generice rule for all .out files.
%.out :
#echo "build $# from $^"
touch $#
%.src : # For debugging only.
touch $#
.PHONY: all
Output:
$ make
touch aaa.src
mkdir aaa
build aaa/aaa.out from aaa.src
touch aaa/aaa.out
touch bbb.src
mkdir bbb
build bbb/bbb.out from bbb.src
touch bbb/bbb.out
touch ccc.src
mkdir ccc
build ccc/ccc.out from ccc.src
touch ccc/ccc.out
Note that it is more efficient and elegant to have order-only dependencies on directories and let make create them, than to have each recipe checking directory existence first.
$make --- Will have normal build
$make CAdvisor
Above will do following steps:
1) Update variable CC, now it should become "cadvise -pdb mypdb +wlint +wall aCC"
2) Run all with updated CC option
CC = aCC
CFLAGS = -c #-Wall
LDFLAGS =
SOURCES = foo.cc
OBJECTS = $(SOURCES:.cc=.o)
EXECUTABLE = observer
RM=rm -rf
CADVISE_OPTS= -pdb mypdb +wlint
CADVISE= /opt/cadvise/bin/cadvise
.PHONY : CAdvisor update_cc clean all
all: $(SOURCES) $(EXECUTABLE)
$(EXECUTABLE): $(OBJECTS)
$(CC) $(LDFLAGS) $(OBJECTS) -o $#
.cc.o:
$(CC) $(CFLAGS) $< -o $#
clean:
$(RM) $(EXECUTABLE) $(OBJECTS)
update_cc: CC := ${$(CADVISE) $(CADVISE_OPTS) $(CC)}
CAdvisor: update_cc all;
#echo DEBD $(CC)
Now above code is giving me error:
**$ make CAdvisor
Make: Don't know how to make CC. Stop.
$**
How to fix this error
Any better option?
Linkes:link_how to call target from another
Thanks
Sorry, but that's not how target-specific variables work. Target-specific variables are scoped to their target and any prerequisite built as a result of building that target. It's not the case that the target-specific setting changes the value of the global variable for the rest of the recipes expanded by make.
In your example, all is not a prerequisite of update_cc, it's a sibling. So, target-specific variables that are set for update_cc have no impact on the all target.
Second, using ${$(CADVISE) $(CADVISE_OPTS) $(CC)} is definitely not right: the inside will be expanded first then because the entire thing is enclosed in ${...} it will be treated as a variable name, and that variable (which clearly doesn't exist) will be looked up, resulting in an empty string.
I don't know why you have added the extra target update_cc at all; why not just set the target-specific variable on the CAdvisor target?
CAdvisor: CC := $(CADVISE) $(CADVISE_OPTS) $(CC)
CAdvisor: all
#echo DEBD $(CC)
I'm learning to write makefiles. I made my own simple one just to try and test, but every time I run make, i get:
make: *** No rule to make target `/%.cpp', needed by `obj'. Stop.
I googled. I'm pretty sure I typed everything correctly, and my folders are set up the way they should be. Here is the makefile:
CC = g++
LD = g++
NAME = app
OBJ_DIR = obj
SRC_DIR = src
CC_FLAGS = -std=c++0x
all: $(NAME)
$(NAME): $(OBJ_DIR)/%.o
$(LD) $(OBJ_DIR)/%.o -o $#
$(OBJ_DIR)/%.o: $(SRC_DIR)/%.cpp
$(CC) $< -o $# $(CC_FLAGS)
clean:
rm $(NAME) $(OBJ_DIR) -rf
What is the problem?
The line:
$(NAME): $(OBJ_DIR)/%.o
is not correct. This is not a pattern rule (because the target doesn't contain a pattern character, %) and so it's interpreted as an explicit rule, saying that app depends on the actual file named obj/%.o which doesn't exist, and make doesn't know how to build it (because there's no file src/%.cpp).
You need to change this to:
$(NAME): $(OBJ_DIR)/foo.o ...
or whatever object files you have.
I am stumped coming up with a makefile rule to have several executables where each depends on its respective source file. There is a library common to all and each program has a single source file: a.c compiled and linked with the library produces executable a, etc.
LIB_C_FILES = f1.c f2.c f3.c
LIB_H_FILES = f1.h f2.h f3.h
TARGETS = a b c
CFLAGS = -g -O0 -DDEBUG
.PHONY : all clean
.c.o:
g++ -c $(CFLAGS) -o $# $<
all: $(TARGETS)
${TARGETS} : lib.a ${#:%=%.c}
g++ $(CFLAGS) ${#:=.c} -o $# lib.a
lib.a: ${LIB_C_FILES:.c=.o} $(LIB_H_FILES)
ar r $# $?
The library portion works fine. And when an executable does not exist, it also works fine. But when one of the standalone source files is modified it says make: Nothing to be done for 'all'.
I don't understand the proper way to make target a depend on source a.c individually in a list. What am I missing?
Just for completeness: you can do what you want with plain old static pattern rules, so long as you can match all of ${TARGETS} with make's (noddy) pattern matching.
${TARGETS}: %: %.C lib.a
g++ ${CFLAGS} $< -o $# lib.a
lib.a: ...
ar ...
A tad more readable, and perhaps more compatible than .SECONDEXPANSION?
First, I assume fio.a was a typo (you probably meant lib.a).
Second, I think the tricky part is your ${#:%=%.c} prerequisite. AFAIK, $# can't be used this way.
I think you can get the behavior you're looking for using .SECONDEXPANSION though.
Try:
.SECONDEXPANSION:
${TARGETS} : lib.a $$(patsubst %,%.c,$$#)
There may be an old-style substitution way to do this, but I find the patsubst line to be more readable than ${#:%=%.c}.
(I should add that this applies to Gnu make 3.82. YMMV with older versions of Gnu make, or [heaven forbid] non-Gnu versions of make).
I'm expecting to see files foo1 and foo3 created by the makefile below. However only a file foo3 is created. To me it seems that the canned recipe make-foo is simply ignored by make. The debug outcome of targets foo1 and foo2 (empty recipe) is identical.
# why canned recipe doesn't work ?
# http://www.gnu.org/software/make/manual/make.html#Canned-Recipes
define make-foo =
echo making $#
touch $#
endef
.PHONY: all
all: foo1 foo2 foo3
# foo1 is not created, but why ?
.PHONY: foo1
foo1:
$(make-foo)
# debug output similar to foo1
.PHONY: foo2
foo2:
# this works
.PHONY: foo3
foo3:
echo making $#
touch $#
Running make:
xxxx#xxxx:/dev/shm$ make -dRr
GNU Make 3.81
Copyright (C) 2006 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.
There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A
PARTICULAR PURPOSE.
This program built for i686-pc-linux-gnu
Reading makefiles...
Reading makefile `makefile'...
Updating makefiles....
Considering target file `makefile'.
Looking for an implicit rule for `makefile'.
No implicit rule found for `makefile'.
Finished prerequisites of target file `makefile'.
No need to remake target `makefile'.
Updating goal targets....
Considering target file `all'.
File `all' does not exist.
Considering target file `foo1'.
File `foo1' does not exist.
Finished prerequisites of target file `foo1'.
Must remake target `foo1'.
Successfully remade target file `foo1'.
Considering target file `foo2'.
File `foo2' does not exist.
Finished prerequisites of target file `foo2'.
Must remake target `foo2'.
Successfully remade target file `foo2'.
Considering target file `foo3'.
File `foo3' does not exist.
Finished prerequisites of target file `foo3'.
Must remake target `foo3'.
echo making foo3
Putting child 0x0914c5f0 (foo3) PID 3132 on the chain.
Live child 0x0914c5f0 (foo3) PID 3132
making foo3
Reaping winning child 0x0914c5f0 PID 3132
touch foo3
Live child 0x0914c5f0 (foo3) PID 3133
Reaping winning child 0x0914c5f0 PID 3133
Removing child 0x0914c5f0 PID 3133 from chain.
Successfully remade target file `foo3'.
Finished prerequisites of target file `all'.
Must remake target `all'.
Successfully remade target file `all'.
Missing foo1:
xxxx#xxxx:/dev/shm$ ll foo*
-rw-r--r-- 1 xxxx xxxx 0 2011-02-17 20:04 foo3
I think you don't want the = at the end of the define line. This makefile works here for me:
define make-foo
echo making $#
touch $#
endef
.PHONY: foo1
foo1:
$(make-foo)
Example:
$ make
echo making foo1
making foo1
touch foo1
$ ls
Makefile foo1
The GNU make manual seems to indicate that the = should be just fine, but like you, I get different behaviour if I have it there.
Edit: I just asked:
GNU make differences in multiline variable declarations
To get some clarification on what's happening here...