VHDL bit aggregation - vector

Question

I have a VHDL design question.
I have N similar entities which take some input and each of them generates
an STD_LOGIC output.
Example:
entity example1 is
begin
...
result_1 : out std_logic;
end example1;
entity example2 is
begin
...
result_2 : out std_logic;
end example2;
...
I am looking for a way to aggregate all those single bit results in one UNSIGNED(N - 1 downto 0) result signal V such that V(i) = result_i holds.
Currently, my approach looks like this:
entity ResultAggregation is
port (
result_1 : in std_logic;
result_2 : in std_logic;
aggregate_results : out unsigned(1 downto 0)
);
end ResultAggregation;
architecture Behavioral of ResultAggregation is
begin
aggregate_results <= result_2 & result_1;
end Behavioral;
I find this approach rather clumsy. What I am looking for is a more automated solution,
for example that I can provide the number N such that the appropriate pins are generated.
I know this is a rather generic question, but if somebody knows a clever solution please
let me know.
Thanks in advance,
Sven

Answer 1

My suggestions would be to omit the ResultAggregation entity and only define a aggregate_results signal on the same level as your example1, example2, etc. entities. You could then instantiate these entities as
i_example1 : entity work.example1
port map (
...
result_1 => aggregate_results(0));
i_example2 : entity work.example2
port map (
...
result_2 => aggregate_results(1));
You could make the width of the aggregate_results vector a generic on the level where you instantiate the example1 etc. entities.
The only way you can get a generic number of pins would be to define your ResultsAggregation entity as
entity ResultAggregation is
generic (
N_RESULTS : integer
);
port (
results : in std_logic_vector(N_RESULTS-1 downto 0);
aggregate_results : out std_logic_vector(N_RESULTS-1 downto 0)
);
end ResultAggregation;
But then this entity would only contain the statement aggregate_results <= results which makes this entity pointless.

Answer 2

use a for/generate statement if blocks are identical:
n_examples: for i in 0 to (N-1) generate
inst_example: example_entity
port map(
...
result => V(i);
);
end generate n_examples;
if blocks have similar entity but different funcitonality, you can still use this approach:
...
inst_ex1: example1
port map(
...,
result_1 => V(1)
);
inst_ex2: example2
port map(
...,
result_2 => V(2)
);
....