Is there a way to write a target to
1) only create object files?
2) only to link object files and create the binary file?
I would like to be able create my binary file in 2 steps.
There is an implicit rule for that. Let's say you have the following Makefile:
CC=cc -g
all: client
client: client.c
$(CC) client.c -o client
clean:
-rm -f client
If you only want the object file, then you just need to run:
$ make client.o
And you will get the object file. However, you can also write an explicit rule, such as:
%.o: %.c
$(CC) -c $<
The previous rule is a rule to build from any .c file to an object (.o) file. $< helps to get the name of file where the rule depends on.
If you have several objects files, you might want to define variables then:
objects = client.o foo.o bar.o
client: $(objects)
$(cc) -o $# $(objects)
$(objects): config.h
clean:
-rm -f client $(objects)
In this case, objects is a variable associated with the object files you want to compile. Which is used in the rule client as a dependency and as argument to link them, it is also used to define rules that depends on header files (config.h in this example), and finalle is used in the clean rule to delete them to start all over again.
$# is a replacement for the name of the rule. In the last case it would be client.
The manual of GNU Make contains a lot of examples that should enlighten your learn process.
Related
A common Makefile for automatically prereq, looks like:
SRCS := $(wildcard *.c)
OBJS := $(SRCS:%.c=%.o)
DEPS := $(OBJS:%.o=%.d)
$(OBJS): %.o: %.c
$(CC) $(CFLAGS) -c -o $# $<
include $(DEPS)
$(DEPS): %.d: %.c
xxx
the first time, build ok, the generated .d file like this:
config.o config.d: config.c config.h
then I rename config.h to config2.h, and modify config.c:
-#include "config.h"
+#include "config2.h"
make again, Makefile generate error:
make[1]: *** No rule to make target 'config.h', needed by 'config.d'
because config.d depends config.h, How can I modify my Makefile to fix this rename problem.
Pretty simple really. Your .d file needs this additional line:
config.h:
Now when make discovers config.h doesn't exist,
it will run the non-existent recipe and happily believe it has created config.h. Then it carries on.
The manual says:
If a rule has no prerequisites or recipe, and the target of the rule is a nonexistent file, then make imagines this target to have been updated whenever its rule is run.
How to we get this extra line?
Back in the day you would run a perl one-liner over the newly created .d file. Nowadays, for modern gcc variants, just add -MP to the compiler command-line.
-MP This option instructs CPP to add a phony target for each dependency other than the main file, causing each to depend on nothing. These dummy rules work around errors make gives if you remove header files without updating the Makefile to match.
Job's a good 'un.
I have a very simple makefile as below:
.PHONY: clean all
CC = /home/utils/gcc-5.2.0/bin/g++
CFLAGS = -Wall -Werror -fPIC
SRC = $(wildcard *.c)
OBJ = $(subst .c,.o,$(SRC))
.INTERMEDIATE: $(OBJ)
all: test.so
%.o: %.c
$(CC) $(CFLAGS) -o $# -c $<
test.so: $(OBJ)
$(CC) -shared $^ -o $#
clean:
#rm -f *.o *~ *.so
I have only two files in the same directory: a.c and b.c
When I execute "make all", I got the following which is perfect.
/home/utils/gcc-5.2.0/bin/g++ -Wall -Werror -fPIC -o a.o -c a.c
/home/utils/gcc-5.2.0/bin/g++ -Wall -Werror -fPIC -o b.o -c b.c
/home/utils/gcc-5.2.0/bin/g++ -shared a.o b.o -o test.so
rm a.o b.o
However, if I do:
touch a.c; make all
I got the same make execution sequence as above which is not what I expected. There is no dependency between a.c and b.c. What I expect is:
/home/utils/gcc-5.2.0/bin/g++ -Wall -Werror -fPIC -o a.o -c a.c
/home/utils/gcc-5.2.0/bin/g++ -shared a.o b.o -o test.so
rm a.o
I don't understand why b.c is compiled again. According to gnumake manual:
The first difference is what happens if the intermediate file does not exist. If an ordinary file b does not exist, and make considers a target that depends on b, it invariably creates b and then updates the target from b. But if b is an intermediate file, then make can leave well enough alone. It won’t bother updating b, or the ultimate target, unless some prerequisite of b is newer than that target or there is some other reason to update that target.
b.o is an intermediate file, it should not be compiled again since b.c has not changed.
What did I miss?
If b.o is not recompiled, then test.so cannot be created because it depends on b.o. You can't create the shared library from a.o and b.o if b.o was deleted.
If you were trying to create a static library then you could use make's special archive syntax to replace a.o without needing to recompile b.o, but that's not possible unless you use the archive special syntax, and it can't be done for shared libraries such as you're trying to build here.
There's a reason these .o files are not considered intermediate by default, and forcing them to be by adding the .INTERMEDIATE target doesn't mean you can avoid rebuilding them.
Your difficulty stems from the fact that what you mean by an intermediate file
is not what GNU Make means; but the .INTERMEDIATE special target allows you to insist
that a.o and b.o, which in your makefile are not intermediate files in GNU Make's
sense, shall be treated as if they are intermediate in GNU Make's sense, and
then you're taken aback by the consequences.
What you mean by F is an intermediate file is: F is a prerequisite of target T and
F itself has prerequisites. Thus a.o and b.o are intermediate with respect to
test.so because they are prerequisites of that target and themselves have the
respective prerequisites a.c and b.c`.
In your sense of intermediate, making the target test.so does not call for
(a.o|b.o) to be remade unless it is older than (a.c|b.c). So you are taken aback by the fact
that when a.o and b.o are made .INTERMEDIATE, GNU Make always deletes them
when it makes test.so:
b.o is an intermediate file, it should not be compiled again since b.c has not changed. What did I miss?
Chiefly you missed 10.4 Chains of Implicit Rules
Ordinarily, a file cannot be intermediate if it is mentioned in the makefile as a target or prerequisite.
However, you can explicitly mark a file as intermediate by listing it as a prerequisite of the special target .INTERMEDIATE.
This takes effect even if the file is mentioned explicitly in some other way.
So, a.o and b.o would ordinarily not be intermediate in GNU Make's sense,
because they are mentioned in your makefile as prequisites of test.so. But you can
make them be treated as intermediate, in GNU Make's sense, by listing them as prerequisites of .INTERMEDIATE - as you did.
What GNU Make means by intermediate is more technical than what you mean and
is explained in the same section of the manual:
Sometimes a file can be made by a sequence of implicit rules. For example, a file n.o
could be made from n.y by running first Yacc and then cc. Such a sequence is called a chain.
If the file n.c exists, or is mentioned in the makefile, no special searching is required:
make finds that the object file can be made by C compilation from n.c; later on, when
considering how to make n.c, the rule for running Yacc is used. Ultimately both n.c and n.o are updated.
However, even if n.c does not exist and is not mentioned, make knows how to envision it as the
missing link between n.o and n.y! In this case, n.c is called an intermediate file.
Once make has decided to use the intermediate file, it is entered in the data base as
if it had been mentioned in the makefile, along with the implicit rule that says how to create it.
(My emphasis). More briefly, if Make is required to make target output, and discovers a file input such
that:
It has no explicit rule for making output from input, but -
It knows a sequence of implicit (a.k.a builtin) rules by
which a file stage that is not a target or prerequisite in the makefile can
be made from input, and from which output can be made, then it will adopt this
sequence of rules to make output from input via stage, and stage will be
an intermediate file.
Crucially, since stage is not one of your targets, or a prerequisite of any of them, Make
knows that it is merely a disposable by-product of making output from input,
and therefore can be deleted when it has served that purpose.
Here is a simple example project involving files that are really intermediate in GNU Make's sense.
We have some yacc source yacc.y and lex source lex.l, in the project directory,
and we want to build a parser from them, parse, with the following makefile:
Makefile
YFLAGS := -d
OBJS := yacc.o lex.o
.PHONY: all clean
all: parse
parse: $(OBJS)
$(CC) $^ -o $#
clean:
$(RM) parse $(OBJS)
It runs like:
$ make
yacc -d yacc.y
mv -f y.tab.c yacc.c
cc -c -o yacc.o yacc.c
lex -t lex.l > lex.c
cc -c -o lex.o lex.c
cc yacc.o lex.o -o parse
rm lex.c yacc.c
Now you see that Make, using its catalogue of implicit rules, figured out
that yacc.o could be made by compiling the non-existent C source file
yacc.c, and that yacc.c could be produced from the existing source file
yacc.y by running yacc -d yacc.y; mv -f y.tab.c yacc.c. Likewise, it figured out that lex.o
could be made by compiling the nonexistent C source lex.c, and that lex.c
could be made from lex.l by running lex -t lex.l > lex.c. Then parse is
made from yacc.o and lex.o by the routine linkage that the makefile
specifies.
But your makefile says nothing whatever about yacc.c and lex.c. As far as
you have told Make, it does not matter to you whether or not such files ever exist.
They are intermediate files, merely stages in the .y -> .o and .l -> .o productions. So
when Make is done with them:
rm lex.c yacc.c
Then if you:
$ touch yacc.y
and again:
$ make
yacc -d yacc.y
mv -f y.tab.c yacc.c
cc -c -o yacc.o yacc.c
cc yacc.o lex.o -o parse
rm yacc.c
only yacc.o gets remade for the linkage of parse, and the one
intermediate file yacc.c that was generated this time is deleted.
Bottom line
Your object files are not intermediate in GNU Make's sense and you don't
want them to be treated as if they are. This is normal for object files.
So remove .INTERMEDIATE: $(OBJ).
Short and easy question, but I seem to have a writer's block here:
Suppose I have a source code file in the same directory as the makefile I use to build the program:
confus#confusion:~/prog$ ls
binaries includes main.c Makefile
How do I get make to put the binaries for my main.c in the binaries dir? Afterwards on a second run make should see if the binary file there is up to date (and don't compile it again) just like normal.
My thought was something like this:
# Makefile
.PHONY: all
SOURCES := $(wildcard *.c)
TARGETS := $(subst %.c,binaries/%.o,$(SOURCES))
all:$(TARGETS)
$(TARGETS):$(SOURCES)
./compile "$(subst .o,.c,$(#F))" -o "$#"
Don't say all targets depend on all sources, instead have a pattern rule
binaries/%.o: %.c
./compile ... -o $# -c $<
you may also need to use a vpath
Revised:
You also had a problem with your subst ...
this test worked (just for compiling individual .o files, you still need to link them, which would be a very simple rule)
# Makefile
.PHONY: all
SOURCES := $(wildcard *.c)
TARGETS := $(patsubst %.c,binaries/%.o,$(SOURCES))
all:$(TARGETS)
binaries/%.o: %.c
$(CC) -o $# -c $<
I'm working on some bare-metal embedded code that runs on ARM, and thus has to deal with the whole ARM vs. THUMB mode distinction. The current build system uses static pattern rules to determine whether to compile files in ARM or THUMB mode.
$(ACOBJS) : %.o : %.c
#echo
$(CC) -c $(CFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $#
$(TCOBJS) : %.o : %.c
#echo
$(CC) -c $(CFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $#
Where ACOBJS is a list of output objects that should be in ARM mode and the same for TCOBJS and Thumb mode. These lists are created from the list of sources in the usual manner of
ACOBJS = $(ACSRC:.c=.o)
TCOBJS = $(TCSRC:.c=.o)
Currently this results in the object files from the build being strewn about the source tree, which I don't particularly desire. I've been trying to set this up for out of tree builds but haven't been able to get this to work. I don't necessarily need to get full out of tree builds working, but I would like to at least be able to use an output directory under which all the intermediate files end up going. What is the best strategy to achieve this under these constraints?
One option I'm considering is using either automake or the whole autotools toolchain to build a makefile. This would seem to support creating the type of makefile I want, but seems like overkill. It also seems like there would be an inherent impedance mismatch between autotools, which is designed for portable builds, and bare-metal embedded systems, where things like host tuple are dictated by the target micro.
This is a bit old but I was just trying to do the same thing this was the first google hit. I thought it was worth sharing another approach since neither answer is convenient if you're not using autotools and want to be able to build in any directory with a single command and later just blow away that directory.
Here's an example of a Makefile that refers to files relative to the directory containing the Makefile.
MAKEFILE_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
MFD := $(MAKEFILE_DIR)
CXX=g++
CXXFLAGS=-std=c++14 -Wall -Wextra -pedantic -c
test: test.o adjacency_pointers_graph.o
$(CXX) $^ -o $#
%.o: $(MFD)/%.cpp $(MFD)/adjacency_pointers_graph.h
$(CXX) $(CXXFLAGS) $< -o $#
Then to do an sort of source build:
mkdir build
cd build
make -f ../Makefile
Considering/assuming you don't care about portability and are using GNU make, you can use the VPATH feature:
Create the directory where you want to do your build.
Create a 'Makefile' in that directory with (approximately) the following contents:
path_to_source = ..
VPATH = $(path_to_source)
include $(path_to_source)/Makefile
Change the path_to_source variable to point to the root of your source tree.
Additionally you probably need to tweak your original Makefile to make sure that it supports the out of source build. For example, you can't reference to prerequisites from your build rules and instead must use $^ and $<. (See GNU make - Writing Recipes with Directory Search) You might also need to modify the vpath-makefile. For example: adding CFLAGS+=-I$(path_to_source) might be useful.
Also note that if a file is in both your source and build directory, make will use the file in your build directory.
On automake
If you use automake, you're pretty much using the entire autotools. automake cannot work without autoconf.
The Makefiles generated by automake support out-of-source builds and cross-compilation, so you should be able to create subdirectories arm/ and thumb/ and run ../configure --host=arm-host-prefix in arm/ and run ../configure --host=thumb-host-prefix in thumb/. (I don't know the actual host tuples that you'd use for each compiler.)
Using GNU make
Since you're using GNUMake, you could do something like this:
ACOBJS := $(addprefix arm/,$(ACSRC:.c=.o))
TCOBJS := $(addprefix thumb/,$(TCSRC:.c=.o))
Use something like this answer to ensure that the arm/ and thumb/ directories (and any subdirectories) exist.
My project needs temporary directories which are created during the build using mkdir -p similarly to this:
all: dirtree $(OBJFILES)
dirtree:
#mkdir -p $(BUILD)/temp_directory
But this approach cannot be used with the -j switch, because first of the OBJFILES get compiled before the mkdir target is made.
Is there a standard way to do this?
The problem with your makefile is that creation of your object files does not depend on creation of the relevant directories (only a phony "all" target does). This kind of dependency is necessary for -j option, and even without it your makefile works only by chance. There are two (right) ways to impose the dependency in question.
Directories as separate targets
You created the target for directory creation; what left is just put it as a prerequisite to object file rule:
$(BUILD)/temp_directory/%.o: %.c | dirtree
$(CC) $^ -o $#
The pipe symbol | means that dirtree is an "order only prerequisite". It is used when "dirtree" is a prerequisite but changes in the dirtree do not invalidate object files and do not affect the outcome of compilation command.
Use of "order-only" prerequisite is important here. The thing is that dirtree target would be remade at each Make invocation. That would cause everything that depends on it be remade as well, so it would rebuild all object files every time.
Create directories in shell commands
Another way is to ensure that the directory is created immediately before you invoke compilation
$(BUILD)/temp_directory/%.o: %.c
#mkdir -p $(#D)
$(CC) $^ -o $#
Note the usage of $(#D). This is expanded as "the directory for the target file". So it may be used uniformly in many places, and even with aid of a variable.
Mkdir=#mkdir -p $(#D)
$(BUILD)/temp_directory/%.o: %.c
$(Mkdir)
$(CC) $^ -o $#
$(INSTALL_DIR)/%: src_dir/%
$(Mkdir)
cp -p $^ $#
Both ways ensure that the directory is created before the compilation commands are invoked. Both ways require you to write some text (either | dirtree or $(Mkdir)) at each rule that needs it. Both ways are -j compatible, but the second solution requires mkdir -p to be thread-safe (as two such commands at once may try to create the same directory, and one of them would fail).
While most systems implement it in such a way that mkdir -p is more or less thread safe, on some systems (as in some Solaris systems, for example), they are less thread-safe than the others. However, even in GNU toolchain mkdir -p may fail if they simultaneously invoke the same mkdir(2) library call.
If you want to be very safe, you can work this around as well. What could be the problem? That two mkdir -p scripts try to create the same directory, and clash somewhere inside C library. Then, one of these mkdir-s will succeed, and the other will fail. However, if the mkdir you invoked failed, then it could be thread-unsafety-related failure only if the directory had been created by a concurrent mkdir. So it would be enough to just check that the target directory is created after mkdir invocation:
Mkdir=#mkdir -p $(#D) || test -d $(#D)
(This solution also has an issue with mode: mkdir may fail when directory exists, but doesn't conform to umask, so you might want to check that as well. But that's too much I guess.)
I'm not sure I fully understand your question. However, I can say this: if your build breaks when you add parallelism, then it's an indication that you haven't defined the dependencies correctly. Ask yourself, "Do the directories need to exist before the object files are generated?" If the answer is "yes", then the directories should be listed as prerequisites of the object files. In other words:
${OBJFILES}: dirtree
And yes, that is pretty much the standard way to do this :)
You could have the rules for building the object files call mkdir -p as their first action.