How to change compiler executable name? I want to perform a "fake build" of some products which are using BJam as build system. (For example: the Boost itself) In this "fake build" I want some special command to be called instead of g++. (with all the options and environment used in real build with real gcc).
How to perform this? Are there any command line switches which already allows me to do what I need or maybe I can somehow modify *.jam files to achieve what I need?
The easiest thing might to just switch your path so gcc refers to what you want to run. Otherwise, the correct way to do it bjam is more finicky. I've never gotten it to successfully, easily work, but here's what the docs suggest:
You'll need to add command to the Jamroot of your project to configure the gcc mocking command. The simplest way is just:
using gcc : : my-gcc ;
But most likely you have another using gcc ; line somewhere in your jam rules (or site-config.jam) and you'll get a complaint about trying to reinitialize a toolset. If so, you'll need to give an explicit version to the toolset like so
using gcc : mywrapper : my-gcc ;
And to use this toolset when compiling use the command bjam toolset=gcc-mywrapper.
Good luck.
Related
I am a little bit confused on how to efficiently prepare the R package, so that it will be compatible across all needed system platforms. This is needed so that the new version of package will be accepted by CRAN. The main difficulty comes from compiling external C++ shared library, and optionally CUDA version if the compiler is available. To support this flow I've created specific Makefile, unfortunately using GNU-extensions. It works fine on Linux, OSX and when executed manually via gmake on Solaris. Relevant part is here:
# Checking whether nvcc compiler is available
NVCC_TEST = $(shell basename $(shell which nvcc 2> /dev/null)"")
ifeq ($(NVCC_TEST),nvcc)
ALL_LIBS += libcucubes_gpu.so
ALL_OBJS += $(GPU_OBJS)
ALL_FLAGS += $(GPU_FLAGS)
else
ALL_OBJS += gpu_fallback.o
endif
Turns out that, when running R CMD INSTALL (...) on Solaris, the installation fails on something like this:
make: Fatal error in reader: Makefile, line 39: Unexpected end of line seen
ERROR: compilation failed for package 'libcucubes'
As it turns out, it is caused by the fact that Solaris' version of make is executed instead of GNU-compatible gmake (I've tested it works fine), even though it is available. My question is whether there is any simple way to force usage of gmake here, for the R package build. In general I know I could use autotools to solve compatibility issues during installation, but it seems to bring too much complexity for that simple case. Any advices will be really appreciated, thanks!
If you can't get your build process to use gmake instead of Solaris's pure POSIX make, you can use this hack:
Make a dedicated directory for this hack: mkdir $HOME/make_hack
Softlink gmake asmakein that directory: ln -s /path/to/gmake $HOME/make_hack/make
Set your PATH: PATH=$HOME/make_hack:$PATH
Now, run your build process using that PATH, and it should use gmake. Hopefully it just uses make from its PATH envval and not some hardcoded full path.
Yeah, it's a hack. But it's probably a lot easier than modifying the build process to use gmake instead of make.
From Writing R Extensions:
If you really must require GNU make, declare it in the DESCRIPTION
file by
SystemRequirements: GNU make
and ensure that you use the value of environment variable MAKE (and
not just make) in your scripts.
configure scripts are the preferred solution though. BTW, in general a Makevars file is also preferred over a full Makefile.
I usually work on visual c++ 2010 for creating console applications as programming problems. There is this submission which requires me to give the source for the file "Makefile" by some command in unix environment
all:
g++ program.cc -o program
since i don't use unix and have never created a "makefile". I don't know how to make this submission. I have read about a makefile which is supposed to give the directions dependencies etc for compiling the program. I am using the header files iostream string and iterator in the program. i have tried the "all:" command . The bash returns command not found.
Can someone help me with this submission? The code is ready but the only thing stopping for submitting is this "makefile". please include the shell commands as well.
You're missing newline and two tabs (yes, you read right, not spaces) after the all: line, something like this:
all:
g++ helloworld.cc -o helloworld
To invoke make, type make in the directory with the Makefile. Dependencies on system headers are usually not considered, if your code has just one file, you can safely ignore that.
I would like to get an idea or reference to compile only subset on the openwrt project.
i am aware of the menuconfig utility but this is not enough for my goal.
i would like to compile only the tool-chain (binutils + gcc + glibc) for a specific target (ar71xx) and also the kernel.
now, after looking in the makefiles etc, i have noticed that most of the work in actually patching the toolchain and the kernel and then compile it. is there any option to stop build process after the patching so i can have only the source code patched and i can write my own make file to compile it?
To prepare (patch) toolchain independently:
make toolchain/{clean,prepare} V=99
To extract the kernel source and patch it:
make target/linux/{clean,prepare} V=99
The patched kernel source will be in build_dir/linux-$(target)/linux-$(version)
I am using qmake to generate MinGW32 Makefiles for a small Qt C++ app we are developing. My problem: all those dual/quad core CPUs are sitting there idly while only one thread is doing the building. In order to parallelize things I tried passing --jobs 4 to make, but the problem is that qmake generates a generic makefile inside of which make gets called again with -f .
Is it possible to force qmake to add options to make when generating the makefile? Or maybe there's another way of setting the option outside of qmake altogether? I can't edit that specific Makefile since it's autogenerated each build.
Abusing $MAKE to pass options does not work in all cases. Oftentimes, (e.g. in the configure script of Qt on Unix), it's enclosed in double quotes ("$MAKE") to allow the command to contain spaces. I know because I used the same trick before it stopped working. Qt Support then suggested (rightfully) to use $MAKEFLAGS as in
set MAKEFLAGS=-j4
make
This works for me:
set MAKE_COMMAND=mingw32-make -j%NUMBER_OF_PROCESSORS%
The generic Makefile uses $(MAKE) when invoking make, so you can overwrite it using environment variables. Something like this should do it:
qmake
make MAKE="mingw32-make -j4"
Replace the values of MAKE as required of course :)
I need something like make i.e. dependencies + executing shell commands where failing command stops make execution.
But more deeply integrated with shell i.e. now in make each line is executed in separate context so it is not easy to set variable in one line and use it in following line (I do not want escape char at end of line because it is not readable).
I want simple syntax (no XML) with control flow and functions (what is missing in make).
It does not have to have support for compilation. I have to just bind together several components built using autotools, package them, trigger test and publish results.
I looked at: make, ant, maven, scons, waf, nant, rake, cons, cmake, jam and they do not fit my needs.
take a look at doit
you can use shell commands or python functions to define tasks (builds).
very easy to use. write scripts in python. "no api" (you dont need to import anything in your script)
it has good support to track dependencies and targets
Have a look at fabricate.
If that does not fulfill your needs or if you would rather not write your build script in Python, you could also use a combination of shell scripting and fabricate. Write the script as you would to build your project manually, but prepend build calls with "fabricate.py" so build dependencies are managed automatically.
Simple example:
#!/bin/bash
EXE="myapp"
CC="fabricate.py gcc" # let fabricate handle dependencies
FILES="file1.c file2.c file3.c"
OBJS=""
# build link
for F in $FILES; do
echo $CC -c $F
if [ $? -ne 0 ]; then
echo "Build failed while compiling $F" >2
exit $?
fi
OBJS="$OBJS ${F/.c/.o}"
done
# link
$CC -o $EXE $OBJS
Given that you want control flow, functions, everything operating in the same environment and no XML, it sounds like you want to use the available shell script languages (sh/bash/ksh/zsh), or Perl (insert your own favourite scripting language here!).
I note you've not looked at a-a-p. I'm not familiar with this, other than it's a make system from the people who brought us vim. So you may want to look over that.
A mix of makefile and a scripting language to choose which makefile to run at a time could do it.
I have had the same needs. My current solution is to use makefiles to accurately represent the graph dependency (you have to read "Recursive make considered harmful"). Those makefiles trigger bash scripts that take makefiles variables as parameters. This way you have not to deal with the problem of shell context and you get a clear separation between the dependencies and the actions.
I'm currently considering waf as it seems well designed and fast enough.
You might want to look at SCons; it's a Make-replacement written in Python.