packed vs unpacked vectors in system verilog - vector

Question

Looking at some code I'm maintaining in System Verilog I see some signals that are defined like this:
node [range_hi:range_lo]x;
and others that are defined like this:
node y[range_hi:range_lo];
I understand that x is defined as packed, while y is defined as unpacked. However, I have no idea what that means.
What is the difference between packed and unpacked vectors in System Verilog?
Edit: Responding to #Empi's answer, why should a hardware designer who's writing in SV care about the internal representation of the array? Are there any times when I shouldn't or can't use packed signals?

Answer 1

This article gives more details about this issue:
http://electrosofts.com/systemverilog/arrays.html, especially section 5.2.
A packed array is a mechanism for subdividing a vector into subfields which can be conveniently accessed as array elements. Consequently, a packed array is guaranteed to be represented as a contiguous set of bits. An unpacked array may or may not be so represented. A packed array differs from an unpacked array in that, when a packed array appears as a primary, it is treated as a single vector.

Answer 2

Before knowing what exactly packed and unpacked arrays are, lets also see how you can know which array is what, just by their declaration.
Packed arrays have an object name comes before size declaration. For example:
bit [3][7] a;
Unpacked array have an object name comes after size declaration. For example:
bit a[3];
Packed array make memory whereas Unpacked dont.
You can access/declare unpacked array like this also
reg unpacked_array [7:0] = '{0,0,0,0,0,0,0,1};
You can mix both packed and unpacked array to make a multidimensional memory. For example:
bit [3:0][7:0]a[2:0].
It makes an array of 4 (i.e. 4*8) bytes with depth of 3.

Answer 3

Packed array are mainly used for effective memory usage when we are writing a [3:0][7:0]A[4:0] which means in 32 bit memory locations 4slices each of 8 bit are packed to form a 32 bit. The right side value means there are 5 such slices are there.

Answer 4

bit[3:0] a -> packed array
The packed array can be used as a full array (a='d1) or just part of an array (a[0]='b1)
bit a [3:0] -> unpacked array
The unpacked array cannot be used as a[0]='b1, it has to be used as full a={8{'b1}}

Answer 5

A good explanation is given at verification academy.
A packed array of n vectors can be imagined as an array of single row and n columns.
Whereas an unpacked array of "n" vectors and "m" unpacked dimensions can be imagined as a matrix/2D array of n columns and m rows.

Answer 6

Unpacked arrays will give you more compile time error checking than packed arrays.
I see unpacked arrays on the port definitions of modules for this reason. The compiler will error if the dimensions of the signal are not exactly the same as the port with unpacked arrays. With packed arrays it will normally just go ahead and wire things the best it can, not issuing an error.

Answer 7

bit a [3:0] -> unpacked array The unpacked array cannot be used as a[0]='b1, it has to be used as full a={8{'b1}}
---> in above statement a[0] ='b1; will work for unpacked array , it won't work where some portion of the unpkd arry[eg logic unpkd [8];] like unpkd = 5'h7; assignment same will work for pkd array
--> unpkd = unpkd +2; won't wok for unpkd will work for pkd