FSM problem vhdl AES encryption not entering in third state? - encryption

Question

I had to code the encryption of AES using VHDL and it should compile to succeed the course!!!
I'm having some troubles , FSM isn't entering in the third state!
THIS is the code of FSM:
-- MOORE
library ieee;
use ieee.std_logic_1164.all;
library LIB_RTL ;
library LIB_AES;
use LIB_AES.crypt_pack.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity FSM is
port (
resetb_i : in std_logic ;
clock_i : in std_logic ;
end_key_expander_i : in std_logic ;
start_i : in std_logic;
enableMixcolumns_o : out std_logic;
enableOutput_o : out std_logic;
enableRoundcomputing_o: out std_logic;
reset_key_expander_o: out std_logic;
round_key_expander_o : out std_logic_vector(3 downto 0);
start_key_expander_o : out std_logic;
done_o : out std_logic );
end entity FSM ;
architecture FSM_arch of FSM is
-- definition du type enumere
type state is (idle , keyexpander , initialround , mainround , lastround, ENCoutput );
-- definition des signaux
signal etat_present , etat_futur : state := idle;
signal init_input : std_logic;
signal count_output : bit4;
signal enable_input : std_logic;
component Counter
port (enable_i : in std_logic;
clock_i : in std_logic;
reset_i : in std_logic;
init_i : in std_logic;
count_o : out bit4);
end component;
begin -- moore_arch
DUT : Counter
port map(
enable_i => enable_input,
clock_i => clock_i,
reset_i => resetb_i,
init_i => init_input,
count_o => count_output
);
seq_0 : process (clock_i , resetb_i )
begin -- process seq_0
if resetb_i = '0' then
etat_present <= keyexpander ;
elsif clock_i' event and clock_i = '1' then
etat_present <= etat_futur ;
end if;
end process seq_0 ;
comb0 : process ( etat_present , start_i , end_key_expander_i ) is
begin -- process comb0
case etat_present is
when idle =>
if (start_i = '1') then
etat_futur <= keyexpander ;
else
etat_futur <= idle ;
end if;
when keyexpander =>
if end_key_expander_i = '1' then
etat_futur <= initialround ;
else
etat_futur <= keyexpander ;
end if;
when initialround =>
if (count_output = "0000") then --round0 : start round execution
etat_futur <= initialround ;
else if count_output > "0000" then
etat_futur <= mainround;
end if;
end if;
when mainround =>
if count_output < "1010" then --round1 to round9 : rounds execution
etat_futur <= mainround ;
else if count_output ="1001" then
etat_futur <= lastround ;
end if;
end if;
when lastround =>
if count_output < "1010" then --round10 : last round
etat_futur <= lastround ;
else if count_output ="1010" then
etat_futur <= ENCoutput ;
end if;
end if;
when ENCoutput =>
if start_i = '0' then
etat_futur <= ENCoutput ;
else
etat_futur <= keyexpander ;
end if;
end case ;
end process comb0 ;
-- Output logic of the VHDL MOORE FSM
comb1 : process ( etat_present )
begin -- proceenableMixcolumns_o : out std_logic;
case etat_present is
when idle => --repos
enableMixcolumns_o <= '0';
enableOutput_o <='0';
enableRoundcomputing_o <='0';
reset_key_expander_o <='0';
round_key_expander_o <=count_output;
start_key_expander_o <='0';
done_o <= '0';
when keyexpander => --start key expander
enableMixcolumns_o <= '0';
enableOutput_o <='0';
enableRoundcomputing_o <='0';
reset_key_expander_o <='0';
round_key_expander_o <= count_output;
start_key_expander_o <='1';
done_o <= '0';
when initialround =>
enableMixcolumns_o <= '0';
enableOutput_o <='0';
enableRoundcomputing_o <='1'; --1 for round0
reset_key_expander_o <='0';
round_key_expander_o <=count_output;
start_key_expander_o <='0';
done_o <= '0';
when mainround =>
enableMixcolumns_o <= '1';
enableOutput_o <='0'; --not done
enableRoundcomputing_o <='0'; --0 for round1-->round9
reset_key_expander_o <='0';
round_key_expander_o <=count_output; --start counting rounds
start_key_expander_o <='0'; --done
done_o <= '0';
when lastround =>
enableMixcolumns_o <= '0';
enableOutput_o <='0'; --not done
enableRoundcomputing_o <='0'; --0 for round10
reset_key_expander_o <='0';
round_key_expander_o <=count_output; --10 rounds
start_key_expander_o <='0'; --done
done_o <= '0';
when ENCoutput =>
enableMixcolumns_o <= '0'; --no mixcolumn last round
enableOutput_o <='1'; --done
enableRoundcomputing_o <='0';
reset_key_expander_o <='1';
round_key_expander_o <=count_output; --reset counting
start_key_expander_o <='0';
done_o <= '1';
end case ;
end process comb1 ;
end architecture FSM_arch;
library ieee;
use ieee.std_logic_1164.all;
library LIB_RTL ;
library LIB_AES;
use LIB_AES.crypt_pack.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity Counter is
port (enable_i : in std_logic;
clock_i : in std_logic;
reset_i : in std_logic;
init_i : in std_logic;
count_o : out bit4);
end Counter;
architecture Counter_arch of Counter is
signal counter_s : bit4;
begin
count_o <= counter_s;
seq_0 : process (clock_i, reset_i,enable_i,init_i) is
begin -- process seq_0
if reset_i = '0' then -- asynchronous reset (active-low)
counter_s <= X"0";
elsif clock_i'event and clock_i = '1' then -- rising clock
if (enable_i = '1') then
if (init_i = '1') then
counter_s <= X"0";
else
counter_s <= counter_s + 1;
end if;
else
counter_s <= counter_s;
end if;
end if;
end process seq_0;
end Counter_arch;
The problem appears in the simulation, I'm having start_key_expander_o <='1'; which means it's in the state keyexpander! And enableRoundcomputing_o <='0'; is always 0 which means it's not entering in state: initialround!
I can't understand my mistake...
library ieee;
use ieee.std_logic_1164.all;
Use ieee.numeric_std.all;
Use ieee.std_logic_unsigned.all;
library LIB_RTL ;
library LIB_AES;
use LIB_AES.crypt_pack.all;
ENTITY FSM_tb IS
END FSM_tb;
ARCHITECTURE FSM_tb_arch OF FSM_tb IS
-- Component Declaration for the Moore FSM
COMPONENT FSM
port (
resetb_i : in std_logic ;
clock_i : in std_logic ;
end_key_expander_i : in std_logic ;
start_i : in std_logic;
enableMixcolumns_o : out std_logic;
enableOutput_o : out std_logic;
enableRoundcomputing_o: out std_logic;
reset_key_expander_o: out std_logic;
round_key_expander_o : out std_logic_vector(3 downto 0);
start_key_expander_o : out std_logic;
done_o : out std_logic );
END COMPONENT;
component Counter
port (enable_i : in std_logic;
clock_i : in std_logic;
reset_i : in std_logic;
init_i : in std_logic;
count_o : out bit4);
end component;
--Inputs
signal clock_input : std_logic := '0';
signal resetb_input : std_logic := '1';
signal end_key_expander_input : std_logic := '0';
signal start_input : std_logic := '1';
signal init_input : std_logic :='0';
signal enable_input : std_logic :='1';
--Outputs
signal enableMixcolumns_output : std_logic;
signal enableOutput_output : std_logic := '0';
signal enableRoundcomputing_output : std_logic := '0';
signal reset_key_expander_output : std_logic := '0';
signal round_key_expander_output : std_logic_vector(3 downto 0) := "0000";
signal start_key_expander_output : std_logic := '0';
signal done_output : std_logic := '0';
signal count_output : bit4;
BEGIN
-- Instantiate the Moore FSM
uut: FSM PORT MAP (
resetb_i => resetb_input,
clock_i => clock_input,
end_key_expander_i => end_key_expander_input,
start_i => start_input,
enableMixcolumns_o => enableMixcolumns_output,
enableOutput_o => enableOutput_output,
enableRoundcomputing_o => enableRoundcomputing_output,
reset_key_expander_o => reset_key_expander_output,
round_key_expander_o => round_key_expander_output,
start_key_expander_o => start_key_expander_output,
done_o => done_output
);
DUT : Counter
port map(
enable_i => enable_input,
clock_i => clock_input,
reset_i => resetb_input,
init_i => init_input,
count_o => count_output
);
-- Clock process definitions
clock_input <= not clock_input after 5 ns;
process
begin
wait until clock_input = '1';
resetb_input <= '0';
wait;
end process;
-- Stimulus process
stim_proc: process
begin
wait until clock_input = '1';
-- e2
end_key_expander_input <= '1' ;
start_input <= '0';
wait for 40 ns;
-- fin
end_key_expander_input <= '0' ;
enable_input <= '0';
init_input <= '1';
start_input <= '0';
wait for 20 ns;
done_output <='1';
-- insert stimulus here
wait;
end process;
END;