unspecified minpoly in singular - linear-algebra

I am learning using singular , and I run the following script in singular
ring A1=(2^3,a),x,dp;
minpoly ;
1*a^3+1*a^1+1*a^0
I am confused by it,
I have not specified a monopoly for A1 rings, but the A1 have a monopoly already.
Does this means that the A1 have only 1 monopoly so we don't need to specify it?
Shengyu Shen

sorry, the script should be :
ring A1=(2^3,a),x,dp;
minpoly ;
and the result of minpoly is :
1*a^3+1*a^1+1*a^0
So where does this minpoly come from?
ShengYu Shen

Related

How to use create-<breeds>-with between two breed turtle agents?

I've been stuck by this issue for a long time. I have two networks in my model, so I want to create different types of links with different breed turtle agentsets.
Let's name the 1st turtle agentset T1 and the 2nd T2, so what I did is the following:
breed [T1s T1]
undirected-link-breed [TL1s TL1]
breed [T2s T2]
undirected-link-breed [TL2s TL2]
;;Got error report
ask T1s [create-TL1s-with other n-of 10 T1s]
The last line gave an error reporting that "You cannot use breeded and unbreeded links in the same world". I'm quite confused about what this means.
And then, I changed the last line to:
ask T1s [create-links-with other n-of 10 T1s]
It worked this time, but if that's the case, how can I define two different types of links, i.e., TL1 and TL2, with different turtle agentsets T1s and T2s?
Can anybody help me out? I really appreciate it!
Thanks
That error means that you've created some links that have no breed (probably with create-link-with) before creating links with a breed, or vice-versa. If you want to use link breeds, you can never use create-link-with, create-link-to, or create-link-from. You must always use create-<breed>-with, create-<breed>-to, and create-<breed>-from.
So, search your code for instances of create-link-with, create-link-to, or create-link-from and either delete them or change them to create-<breed>-with, create-<breed>-to, or create-<breed>-from. If you're still getting the error, call clear-all or clear-links to make sure you've removed all unbreeded links.

Prolog out of local stack space/ infinite recursion

I have read other similar questions and answers on this site, but can't seem to find the answer to my particular problem. I am trying to encode a maze in Prolog.
From region 0, you can move freely to regions 1 or region 3. From region 3, you can move freely to region 0, region 4, or region 5, etc. I want to find the all paths of length 7 from the beginning to the end (from 0 to 14). I have encoded the problem in the following manner in SWI-Prolog:
region(0).
region(1).
region(2).
region(3).
region(4).
region(5).
region(6).
region(7).
region(8).
region(9).
region(10).
region(11).
region(12).
region(13).
region(14).
region(15).
connection(0,1). %connection exists between these two regions
connection(0,3).
connection(1,2).
connection(1,8).
connection(1,7).
connection(3,4).
connection(3,5).
connection(7,9).
connection(7,5).
connection(7,8).
connection(5,6).
connection(8,10).
connection(8,11).
connection(11,12).
connection(11,13).
connection(13,15).
connection(13,14).
double_link(X,Y) :-
region(X),
region(Y),
( connection(X,Y) | connection(Y,X) ). %can go from region X to region Y, and vice versa
path(X,Y) :-
double_link(X,Y).
path(X,Y) :-
double_link(X,Z),
path(Z,Y).
When I execute path(14,0). I get true. However, when I execute path(0,14)., I run out of local stack space. I don't know how that can be. Thanks for any help!
You said:
When I execute path(14,0). I get true.
That is half of the truth! Oh, even less than that! In fact you get true not once but many times!
?- path(14,0).
true
; true
; true
; true
; true
; true
; ... .
There is a simple way to avoid typing ; or SPACE all the time. Simply use the goal false.
?- path(14,0), false
loops.
And now, you can also add such false-goals into your program. In this manner you are ruling out parts of the program ; and if the remaining part still loops, you know that there must be a problem there. This is what I got:
region(0) :- false.
% ...
region(12) :- false.
region(13).
region(14).
region(15) :- false.
connection(0,1) :- false.
% ...
connection(13,15) :- false.
connection(13,14).
double_link(X,Y) :-
region(X),
region(Y),
( connection(X,Y) ; connection(Y,X) ).
path(X,Y) :- false,
double_link(X,Y).
path(X,Y) :-
double_link(X,Z),
path(Z,Y), false.
So in this remaining part that loop has to be addressed. It should be now self-explanatory, isn't it?
The problem arises because you can go in circles in the maze. E.g. in your maze you have the connections 0 - 1 - 7 - 5 - 3 - 0. You have not taken any measures to ensure that the search does not follow those circles blindly.
A usual approach would be to add an argument to your path predicate that contains the already visited regions (initially empty). Then you have to ensure when you go to a new location X that X is not in that list (e.g. with nonmember(X,Visited)).

running COBOL program error - mfcobol, CALL ... RETURNING

i got a problem with simple cobol call - returning test program.
I am using micro focus cobol.
here are my 2 codes.
***************** CALLING PROGRAM
IDENTIFICATION DIVISION.
PROGRAM-ID. callreturning.
ENVIRONMENT DIVISION.
DATA DIVISION.
WORKING-STORAGE SECTION.
01 VA PIC S9(8) USAGE DISPLAY.
01 VB PIC S9(8) USAGE DISPLAY.
01 VC PIC 9(4) USAGE DISPLAY value 0.
PROCEDURE DIVISION.
MOVE 1 TO VA.
MOVE 2 TO VB.
move 3 to VC.
CALL "add_two" USING VA VB returning VC.
* DISPLAY VA VB VC.
EXIT PROGRAM.
END PROGRAM callreturning.
*********CALLED PROGRAM
IDENTIFICATION DIVISION.
PROGRAM-ID. add_two.
ENVIRONMENT DIVISION.
DATA DIVISION.
LINKAGE SECTION.
01 PARM_A PIC S9(8) USAGE DISPLAY.
01 PARM_B PIC S9(8) USAGE DISPLAY.
01 PARM_C PIC 9(4) USAGE DISPLAY value 0.
PROCEDURE DIVISION USING PARM_A PARM_B returning PARM_C.
move 3 to PARM_C.
* ADD PARM_A TO PARM_B GIVING PARM_C.
goback.
END PROGRAM add_two.
CALLING program simply calls the second program with using returing value.
But when i compile both program and run, error happens.
error code: 114, pc=0, call=1, seg=0
114 Attempt to access item beyond bounds of memory (Signal 11)
Did i make a wrong code? or other problem? please help me :)
I am testing 'RETURNING' phrase
Your program compiles and works just fine if you get rid of the returning statement.
Background
01 levels defined in the linkage section are more like pointers in a C program. For normal parameters they are set by the calling program. But returning parameters will be unassigned.
The error is probably caused by trying to use an unallocated pointer.
Solution
Do not use returning as it is for working with languages like java.
Allocate storage to the return-value before using it.
See:
Microfocus Manual, Look at the returning example
IBM Manual Look at the Returning Phrase Section
Finally, returning is for working with java. Anything "type" defined on returning should be java compatible (i.e. binary-long and not 9(4)). I strongly suggest not using Returning in Cobol unless you are calling other languages.
Old Question, so i try a short Answer:
First, there is nothing wrong with using returning in MF-COBOL.
So, this is native COBOL (NetExpress as IDE, i assume). To correct ist just change the second Program:
Move PARM_C from the linkage to the working-storage section
The Procedure Division doesn't get the returning Phrase in its opening declaration. Move it instead to the goback phrase:
PROCEDURE DIVISION USING PARM_A PARM_B.
*>...
goback returning PARM_C.

Scilab Error 10000

Hi I am new to scilab and don't have much mathematical background.
I have been following code for another example and am being shown error 10000 for the following code:
function [z]=f(x,y)
z=0.026*(1.0-(y/ym))*y;
endfunction;
ym=12000;
x0=1950;y0=2555;xn=5;h=10;
x=[x0:h:xn];
y=ode("rk",y0,x0,x,f);
disp("x y")
disp("--------")
disp([x'y']);
function z=fe(x)
z=ym/(1-(1-ym/y0)*e^(-k*(t-t0)));
endfunction;
xe=(x0:h/10:xn);
n=length(xe)
for i=1:n
ye(i)=fe(xe(i));
end;
plot (x,y,'ro',xe, ye,'-b');legend ('rk4','Exact',3);
xtitle('solving dy/dx=k(1-y/ym)y','x','y');
I have worked through several other error messages. I am lost and don't know if the problem is in the code or the way I set up the problem. The following is the current error message:
!--error 10000
plot: Wrong size for input argument #2: A non empty matrix expected.
at line 57 of function checkXYPair called by :
at line 235 of function plot called by :
plot (x,y,'ro',xe, ye,'-b');legend ('rk4','Exact',3);
at line 25 of exec file called by :
I would appreciate any help.
Thanks
Start by adding clear as first statement, this will erase all variables before running your function. In the above script you don't declare ye.
Also the statement x=[x0:h:xn]; is strange with those values for x0,h and xn. You are now trying to get a list of x-values starting at 1950 and with positive steps of 10 up until 5 is reached.
I would recommend to try each line and see if the outcome is as expected. You do not need to know everything about the code, but probaly x and y should contain at least some values. The error is telling you that it expected a non-empty matrix for argument 2. This is y, so essentially it is telling you y is empty.

Spartan 3 Starter Kit Constraints File

I am not sure if this is the right stack exchange website to post this on, but if it isn't please move it to the appropriate one.
I am facing a small problem in writing my constraints file for the spartan 3 starter kit.
I have read the documentation provided by Xilinx (the manufacturer) and ive been searching online for a few weeks without any luck.
What i am trying to do is link my Netlist interface to any of the 3 40-pin-headers on the board. (See image below)
Usually its very simple, if say i want to interface a button or a led on the board, i just read the connection name on the board, for example one of the buttons is M13 and write in the UCF file something like this :
NET "BTN0" LOC = "M13";
As you can see on the image the headers are named A1, A2 and B1 on the board, but oddly enough, none of the following worked :
NET "TestOutputLine" LOC = "A1(0)"; -- The (0) is to reference a single line on an array
NET "TestOutputBus" LOC = "A1"; -- The bus is of equal dimension of A1 (which is 40)
The errors i got meant that either the target (specified by LOC) does not exist or that the assignment is invalid.
I hope you have some ideas for me.
Thanks in advance
EDIT :
Here is the output from ISE :
ConstraintSystem:59 - Constraint <NET "TestOutputBus" LOC = "A1";>
[circuit.ucf(12)]: NET "TestOutputBus" not found. Please verify that:
1. The specified design element actually exists in the original design.
But i am pretty sure that TestOutputBus exists, as a matter of fact there is nothing else in my design right now, and the correct top level unit is being used.
EDIT2 :
I updated my UCF file, right now it's like this :
NET "TestOutputBus(0)" LOC = "A1(0)";
NET "TestOutputBus(1)" LOC = "A1(1)";
But i get a different error now in mapping :
MapLib:30 - LOC constraint A1:0 on TestOutputBus<0> is invalid: No such
site on the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
MapLib:30 - LOC constraint A1:1 on TestOutputBus<1> is invalid: No such
site on the device. To bypass this error set the environment variable
'XIL_MAP_LOCWARN'.
Solution :
In order to get the pins 5 and 6 mapped to TestOutputBus(0) and TestOutputBus(1) respectively what i had to use was this :
NET "TestOutputBus(0)" LOC = "N7"; -- A1 pin 5
NET "TestOutputBus(1)" LOC = "L5"; -- A1 pin 6
Note that pins 0 are not mappable thats why i used pins 5 and 6, here are the tables that show the mappable pins for all headers and their LOCs.
As it turns out, there is an address for each usable pin of each header of the FPGA.
The datasheet (http://forums.xilinx.com/xlnx/attachments/xlnx/Spartan/3411/1/S3BOARD_RM.pdf) was helpful especially pages 49 - 51
I copied this from my earlier comment to your question so it would be an actual answer and not just a comment.
You should have LOC constraints in your UCF file for every port on your top-level module. So if you have a 40-bit-wide bus as an input or output at the top level then you should also have 40 separate LOC constraints in your UCF file to make sure that the logical bus in your top-level schematic actually gets mapped to the correct pins on your FPGA. If you are only using two pins, then you can declare the bus to be 2-bits wide and use 2 LOC constraints. The FPGA will treat all unused pins as inputs and ignore them.
I once got the original ConstraintSystem:59 net xyz not found error when i accidentally selected one of my modules as a top module. The pins declared in UCF could not be found in the port declaration of wrong module.
Also i get this error when i have some pin declared in UCF but ommit it in port declaration of top module.

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