I have a following scenario in my build system.
1. 1000 makefiles in src directories
2. There is common.make file being included for all 1000 makefiles
3. links were created for makefiles and sources in object directory from source directory. Hence all makefiles and many more scripts inside makefile are written in such a way as it exists in build directory.
4. obj directory is the dynamic location.
5. Now I removed all links.no more links in object directory.
6. I want to execute all makefiles in source directory where I expect to change the object directory (dynamic directory name) before executing. (I can't use make -C here, because I do not know what directory to change). I can set VPATH for finding sources.
7. I want to make use common.make to change the directory dynamically, but whatever cd, $(shell cd ...) I do in common.make is not reflected in main Makefile.
8. If I do not do this, I will end up in modifying all 1000 makefiles. I do not want to do this.
Please let me know the best of way of doing it. In simple words, I want to change the directory (through common.make) before executing my 1000 makefiles,
I expect common.make to do the following.
1) save srcpath = current path (current path is source directory)
2) Change to output directory (Directory name is dynamic here).
3) set VPATH=srcpath
4) now any makefile in source directory can make use of common.make to compile and have the binaries and objects in output directory.
# This is one of the sample Makefile. I have shortened this file. All makefiles are not using the same names like SRCS, CMDSRCS. It would be different.
# this is existing makefile. Source location /home/user/project/src/mod1/lib/resmgr>make BD=100. I want the output to
# /home/user/project/build/swout100/mod1/lib/resmgr/*. common.make (common make) might validate the argument BD here. BD=101 is not allowed.
# We can force the user to do make -C /home/user/project/build/swout100/mod1/lib/resmgr (no BD validation here. user should know what directory to go).
# I would expect common.make would help the user as utility makefile
TOPDIR = ../../..
MAKEDIR = $(TOPDIR)/make
include $(MAKEDIR)/common.make # It is included in most makefiles. This can be treated as common makefile. I thought of modifying common.make
include ........ #(More includes here)
TARGET = resmgrd
CMDSRCS = resmgr_cli.c \
resmgrlogshow.c \
# more source files here
CMDOBJS = $(CMDSRCS:.c=.o)
CMDHNDLR = resmgrcmd
#... CFLAGS here and library flags here
MDSRC = main.c
SRCS = resmgr.c \
# more source files here
HDRS = resmgr.h
MDOBJ = $(MDSRC:.c=.o)
OBJS = $(SRCS:.c=.o)
$(OBJS) $(MDOBJ) $(CMDOBJS): $(HDRS)
DEPENDSRCS = $(MDSRC) $(SRCS) $(CMDSRCS)
ST_LIBS = $(DEVOSLIBSRC)/apixdr/libapixdr.a
$(TARGET): $(MDOBJ) $(OBJS)
$(CC) $(LDFLAGS) -o $# $^ $(LDLIBS) $(ST_LIBS)
$(CMDHNDLR): $(CMDOBJS)
$(CC) $(LDFLAGS) -o $# $^ $(DEVOSLIBS) $(IPCLIB) $(KILIB) $(MIAUXLIB) \
$(RESMGRLIB) $(RBACLIB)
install:: install-server
install-server: $(TARGET) $(TARGET).options $(DEVOSSBINDIR) $(DEVOSCONFDIR)
$(INSTALL) -m 755 $(TARGET) $(DEVOSSBINDIR)
install-commands: $(DEVOSBINDIR)/$(CMDHNDLR) \
install-admin-cmds install-user-cmds
clean::
$(RM) $(OBJS) $(TARGET) $(SCRIPTS) $(RAWMAN) $(CMDHNDLR) $(ZIPMAN)
I found an answer to my question.
http://make.paulandlesley.org/multi-arch.html
Related
I'm using a find command in a makefile like so:
CC = clang++
CODE = $(shell find . -name *.cpp) #find command here !!!!!!
EXEC = tcr_translator
.PHONY: all clean
all: $(OBJECT)
clear
$(CC) $(CODE) -o $(EXEC) -I src/
clean:
rm $(EXEC)
run: all
./tcr_translator
So, this find command list all the cpp file to compile, makes it easier than to hard-write them in my makefile. This worked perfectly for my last project, so I took the same makefile for my new project. My problem, now the find command (which is, char for char, the same command) won't look into my subdirectories.
So if I have .cpp in a src/ subfolder, it won't find them.
Why would such a command work in a certain directory and not in an other. I'm really at a loss here :(
You should quote the *.cpp to avoid it from being expanded by shell before passed into find.
CODE = $(shell find . -name '*.cpp')
Is there a way to write a target to
1) only create object files?
2) only to link object files and create the binary file?
I would like to be able create my binary file in 2 steps.
There is an implicit rule for that. Let's say you have the following Makefile:
CC=cc -g
all: client
client: client.c
$(CC) client.c -o client
clean:
-rm -f client
If you only want the object file, then you just need to run:
$ make client.o
And you will get the object file. However, you can also write an explicit rule, such as:
%.o: %.c
$(CC) -c $<
The previous rule is a rule to build from any .c file to an object (.o) file. $< helps to get the name of file where the rule depends on.
If you have several objects files, you might want to define variables then:
objects = client.o foo.o bar.o
client: $(objects)
$(cc) -o $# $(objects)
$(objects): config.h
clean:
-rm -f client $(objects)
In this case, objects is a variable associated with the object files you want to compile. Which is used in the rule client as a dependency and as argument to link them, it is also used to define rules that depends on header files (config.h in this example), and finalle is used in the clean rule to delete them to start all over again.
$# is a replacement for the name of the rule. In the last case it would be client.
The manual of GNU Make contains a lot of examples that should enlighten your learn process.
Short and easy question, but I seem to have a writer's block here:
Suppose I have a source code file in the same directory as the makefile I use to build the program:
confus#confusion:~/prog$ ls
binaries includes main.c Makefile
How do I get make to put the binaries for my main.c in the binaries dir? Afterwards on a second run make should see if the binary file there is up to date (and don't compile it again) just like normal.
My thought was something like this:
# Makefile
.PHONY: all
SOURCES := $(wildcard *.c)
TARGETS := $(subst %.c,binaries/%.o,$(SOURCES))
all:$(TARGETS)
$(TARGETS):$(SOURCES)
./compile "$(subst .o,.c,$(#F))" -o "$#"
Don't say all targets depend on all sources, instead have a pattern rule
binaries/%.o: %.c
./compile ... -o $# -c $<
you may also need to use a vpath
Revised:
You also had a problem with your subst ...
this test worked (just for compiling individual .o files, you still need to link them, which would be a very simple rule)
# Makefile
.PHONY: all
SOURCES := $(wildcard *.c)
TARGETS := $(patsubst %.c,binaries/%.o,$(SOURCES))
all:$(TARGETS)
binaries/%.o: %.c
$(CC) -o $# -c $<
I'm working on some bare-metal embedded code that runs on ARM, and thus has to deal with the whole ARM vs. THUMB mode distinction. The current build system uses static pattern rules to determine whether to compile files in ARM or THUMB mode.
$(ACOBJS) : %.o : %.c
#echo
$(CC) -c $(CFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $#
$(TCOBJS) : %.o : %.c
#echo
$(CC) -c $(CFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $#
Where ACOBJS is a list of output objects that should be in ARM mode and the same for TCOBJS and Thumb mode. These lists are created from the list of sources in the usual manner of
ACOBJS = $(ACSRC:.c=.o)
TCOBJS = $(TCSRC:.c=.o)
Currently this results in the object files from the build being strewn about the source tree, which I don't particularly desire. I've been trying to set this up for out of tree builds but haven't been able to get this to work. I don't necessarily need to get full out of tree builds working, but I would like to at least be able to use an output directory under which all the intermediate files end up going. What is the best strategy to achieve this under these constraints?
One option I'm considering is using either automake or the whole autotools toolchain to build a makefile. This would seem to support creating the type of makefile I want, but seems like overkill. It also seems like there would be an inherent impedance mismatch between autotools, which is designed for portable builds, and bare-metal embedded systems, where things like host tuple are dictated by the target micro.
This is a bit old but I was just trying to do the same thing this was the first google hit. I thought it was worth sharing another approach since neither answer is convenient if you're not using autotools and want to be able to build in any directory with a single command and later just blow away that directory.
Here's an example of a Makefile that refers to files relative to the directory containing the Makefile.
MAKEFILE_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
MFD := $(MAKEFILE_DIR)
CXX=g++
CXXFLAGS=-std=c++14 -Wall -Wextra -pedantic -c
test: test.o adjacency_pointers_graph.o
$(CXX) $^ -o $#
%.o: $(MFD)/%.cpp $(MFD)/adjacency_pointers_graph.h
$(CXX) $(CXXFLAGS) $< -o $#
Then to do an sort of source build:
mkdir build
cd build
make -f ../Makefile
Considering/assuming you don't care about portability and are using GNU make, you can use the VPATH feature:
Create the directory where you want to do your build.
Create a 'Makefile' in that directory with (approximately) the following contents:
path_to_source = ..
VPATH = $(path_to_source)
include $(path_to_source)/Makefile
Change the path_to_source variable to point to the root of your source tree.
Additionally you probably need to tweak your original Makefile to make sure that it supports the out of source build. For example, you can't reference to prerequisites from your build rules and instead must use $^ and $<. (See GNU make - Writing Recipes with Directory Search) You might also need to modify the vpath-makefile. For example: adding CFLAGS+=-I$(path_to_source) might be useful.
Also note that if a file is in both your source and build directory, make will use the file in your build directory.
On automake
If you use automake, you're pretty much using the entire autotools. automake cannot work without autoconf.
The Makefiles generated by automake support out-of-source builds and cross-compilation, so you should be able to create subdirectories arm/ and thumb/ and run ../configure --host=arm-host-prefix in arm/ and run ../configure --host=thumb-host-prefix in thumb/. (I don't know the actual host tuples that you'd use for each compiler.)
Using GNU make
Since you're using GNUMake, you could do something like this:
ACOBJS := $(addprefix arm/,$(ACSRC:.c=.o))
TCOBJS := $(addprefix thumb/,$(TCSRC:.c=.o))
Use something like this answer to ensure that the arm/ and thumb/ directories (and any subdirectories) exist.
I am using cmake to build my project. For UNIX, I would like to type make from my project's root directory, and have cmake invoked to create the proper Makefiles (if they don't exist yet) and then build my project. I would like the cmake "internal" files (object files, cmake internal Makefiles, etc.) to be hidden (e.g. put in a .build directory) so it doesn't clutter my project directory.
My project has several sub-projects (in particular, a library, a user executable, and a unit test executable). I would like Makefiles (i.e. I type make and this happens) for each sub-project to execute cmake (as above) and build only that sub-project (with dependencies, so the library would be built from the executables' Makefiles, if needed). The resulting binary (.so library or executable) should be in the sub-project's directory.
I made a Makefile which does the main project bit somewhat well, though it feels somewhat hackish. I can't build specific targets using it, because my Makefile simply calls make in cmake's build directory.
Note that because the library is a sole dependency (and probably doesn't need to be build manually, and because I'm lazy) I omitted it in my Makefile.
BUILD_DIR := .build
.PHONY: all clean project-gui ${BUILD_DIR}/Makefile
all: project-gui project-test
clean:
#([ -d ${BUILD_DIR} ] && make -C ${BUILD_DIR} clean && rm -r ${BUILD_DIR}) || echo Nothing to clean
project-gui: ${BUILD_DIR}/Makefile
#make -C ${BUILD_DIR} project-gui
#cp ${BUILD_DIR}/project-gui/project-gui $#
project-test: ${BUILD_DIR}/Makefile
#make -C ${BUILD_DIR} project-test
#cp ${BUILD_DIR}/project-test/project-test $#
${BUILD_DIR}/Makefile:
#[ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR}
#[ -f ${BUILD_DIR}/Makefile ] || (cd ${BUILD_DIR} && cmake ${CMAKE_OPTS} ..)
If it helps, here's my project structure (if this is "wrong" please tell me -- I'm still learning cmake):
project/
project/CMakeLists.txt
project/common.cmake
project/Makefile -- see Makefile above for this; should be replaced with something better, building libproject, project-gui, and project-test
project/libproject/
project/libproject/CMakeLists.txt
project/libproject/libproject.so -- after build
project/libproject/Makefile -- doesn't exist yet; should build libproject only
project/libproject/source/
project/libproject/include/
project/project-gui/
project/project-gui/CMakeLists.txt
project/project-gui/Makefile -- doesn't exist yet; should build libproject then project-gui
project/project-gui/source/
project/project-gui/include/
project/project-test/
project/project-test/CMakeLists.txt
project/project-test/Makefile -- doesn't exist yet; should build libproject then project-test
project/project-test/source/
project/project-test/include/
If you haven't caught on yet, I'm basically looking for a way to build the project and sub-projects as if cmake wasn't there: as if my project consisted of only Makefiles. Can this be done? Is the solution elegant, or messy? Should I be trying to do something else instead?
Thanks!
If cmake is generating the makefiles, you can simply include the generated makefile in the master makefile, eg
# makefile
all: # Default
include $GENERATED
$GENERATED:$CMAKEFILE
# Generate the makefile here`
The included files are generated then make is restarted with the new included files. The included files should detail the targets, etc.
You should be able to change the location of used files using the vpath directive, see e.g. the Gnu make manual,
vpath %.o project/.build
else the tedious way is to rewrite the rules making note of the necessary directory.
Ed:
Perhaps we shouldn't use a flat makefile.
Try something like:
# makefile
all: gui test
clean:
$(MAKE) -f $(GUI-MAKE) clean
$(MAKE) -f $(TEST-MAKE) clean
gui:$(GUI-MAKE)
$(MAKE) -f $(GUI-MAKE) all
$(GUI-MAKE):$(GUI-CMAKE)
# Generate
# Same for test
This should work if the $(MAKE) -f $(GUI-MAKE) all command works on the command line, and we've hidden cmake in the generating target. You would have to copy any other targets to the master makefile as well, and take care running make in parallel.
Propagating object files through should involve something like
%.o:$(GUI-MAKE)
$(MAKE) -f $(GUI-MAKE) $#
although you'll probably get errors trying to make test objects