Writing your Own Makefile - unix

Question

I am trying to write a Makefile but it is showing
Make: Don't know how to make cc. Stop.
what I am doing is this :-
Hello.c
#include<stdio.h>
extern int print();
int main(){
print();
return 0;
}
print.c
#include<stdio.h>
int print(){
printf("hello\n");
return 0;
}
Makefile
all: OUT
OUT: cc Hello.o print.o -o OUT
Hello.o: Hello.c\
cc -c Hello.c
print.o: print.c \
cc -c print.c
clean: rm -f *.o
clobber: rm -f OUT
when I am writing make
$>make
Make: Don't know how to make cc. Stop.
$>make clean
Make: Don't know how to make rm. Stop.
what thing I am missing..
I am newbie with this make and makefile, so please suggest me some good tutorials on this
I changed to this :-
all: OUT
OUT:; #cc Hello.o print.o -o OUT
Hello.o:; #cc -c Hello.c
print.o:; #cc -c print.c
clean:; #rm -f *.o
clobber:; #rm -f OUT
showing error:-
cc: warning 1913:Hello.o' does not exist or cannot be read
cc: warning 1913: print.o' does not exist or cannot be read
ld: I/O error, file "Hello.o": No such file or directory
Fatal error.
*** Error exit code 1

Answer 1

The rules must be on a different line than the targets, indented with a hard tab:
all: OUT
OUT: Hello.o print.o
cc Hello.o print.o -o OUT
Hello.o: Hello.c
cc -c Hello.c
print.o: print.c
cc -c print.c
clean:
rm -f *.o
clobber:
rm -f OUT
But this can be simplified by relying on implicit rules and generalized by using some variables:
all: OUT
OUT: Hello.o print.o
$(CC) $(CFLAGS) $^ -o $#
clean:
rm -f *.o
clobber:
rm -f OUT