Clarification on Ethernet, MII, SGMII, RGMII and PHY - networking

Question

I primarily come from an Embedded Software background and hence I have very limited knowledge about hardware in general. I always use to think Ethernet as that little physical connector on your computer into which you attach your Ethernet cable. And from a Software perspective all you need to do is to install the driver (in Windows) or configure the Linux kernel to include the driver for your Ethernet.
Questions:
But as I have started going down one level (towards the hardware) and looking at various datasheet and schematics, I have started to come across terms like PHY, MII, SGMII, RGMII, etc. And now I am little confused as to what constitutes an Ethernet? For example, when I say Intel 82574L 1.0 Gbps Ethernet port, where do all these terms fit in?

Answer 1

Some definitions:
MAC - media access controller. This is the part of the system which converts a packet from the OS into a stream of bytes to be put on the wire (or fibre). Often interfaces to the host processor over something like PCI Express (for example).
PHY - physical layer - converts a stream of bytes from the MAC into signals on one or more wires or fibres.
MII - media independent interface. Just a standard set of pins between the MAC and the PHY, so that the MAC doesn't have to know or care what the physical medium is, and the PHY doesn't have to know or care how the host processor interface looks.
The MII was standardised a long time ago and supports 100Mbit/sec speeds. A version using less pins is also available, RMII ('R' for reduced).
For gigabit speeds, the GMII ('G' for gigabit) interface is used, with a reduced pincount version called RGMII. A very reduced pincount version called SGMII is also available ('S' for serial) which requires special capabilities on the IO pins of the MAC, whereas the other xMIIs are relatively conventional logic signals.
There are also many more varieties of interfaces used in other circumstances, may of which are linked to from the Wikipedia MII page:
http://en.wikipedia.org/wiki/Media_Independent_Interface
Regarding your specific Intel chip question - as far as I can tell (the datasheet link seems dead), that chip is a MAC, with PCIe. So it will sit between the PCIe bus on the host and some kind of gigabit physical layer (PHY).

Answer 2

Let me try to explain:
The MII, SGMII, RGMII are three kinds of interface between the MAC block and the PHY chip. The Intel 82574L is one MAC chip. Looking following figure:
_______ __________ ___________
CPU | PCI-E | | MII/SGMII/RGMII | |
or |<=======>| MAC |<================>| PHY |<====>physical interface
board| or else | | | |
_______ __________ ___________
For details about MII (100Mbps), SGMII (1Gbps, serial), RGMII (1Gbps, reduced) definition, you can google them.
Basically speaking, NIC (Network Interface Card) consist of one MAC block and related PHY chip, and other peripheral modules. And also one Ethernet device driver should work with the NIC hardware. The MAC block has one interface with the control CPU or PC main-board, such as PCIe bus or else.

Answer 3

You might want to look for the term "7 Layers of OSI" in which some frequently heard terms;
Ethernet PHY Corresponds to Physical Layer which consists from the literally physical components of the communication.
Ethernet MAC (not the Mac Address but the Media-Access Controller) Corresponds to Data-Link Layer, which is responsible from arranging the frames before sending them to physical layer.
Configurations such as MII, RMII, Auto-Negotion are configured from these two.And there are libraries to make your life easy.
Network Layer is the one responsible from routing of the packets. Protocols such as IP and DHCP are considered to be in this layer. Also this layer is the first lowest layer that is solely software based. If you are using light-weight IP for example ip & netif libraries are the ones everything else build upon.
Transport Layer is where transmission protocols such as TCP & UDP can be found.
Hope it helps, I don't know much about the upper layers sadly.

Answer 4

The Intel 82574L chip contains both the MAC and the PHY.
Refer to the Architecture block diagram on page 15 in the datasheet available from here: https://ark.intel.com/content/www/us/en/ark/products/32209/intel-82574l-gigabit-ethernet-controller.html
The MAC and PHY are both there, but from my non-engineer view, I was confused about the MII connections because I was expecting two separate chips.

Answer 5

In very basic terms when you connect ethernet cable to you laptop you are able to access internet. The ethernet port is the interface in above example. Likewise there is an interface connecting your Ethernet Media Access Control(MAC) to Ethernet PHY. Let me break it down here Ethernet MAC is address of NIC(Network interface Card). Ethernet PHY is the physical layer which acts as interface between your ethernet port and Ethernet MAC. Now the Ethernet MAC takes packer from processor converts it into bits and Ethernet PHY convert bits into electrical signals. The interface between the MAC and PHY is where MII/RGMII(etc) comes into picture.
Being media independent means that different types of PHY devices for connecting to different transmission media (i.e. twisted pair, fiber optic, etc.) can be used without redesigning or replacing the MAC hardware. Thus any MAC may be used with any PHY, independent of the network signal transmission media.

Answer 6

SoCs/PCs may have the number of Ethernet ports. For each Ethernet supported device you will have Either SGMII, RGMII interfaces for the data stream. And, you will also have MDIO/MDC interfaces that are used by the drivers on the SoC to control BOTH your MAC and PHY chips if separate (PHY can be SFP or small form factor pluggable).
Combined MAC/PHY chips that work directly with the SoC/CPU to provide both data path & control, as well as PHY (electrical or optical signaling). The MAC part validates packets CRC - counts errored frames, and runts, and provides VLAN capability and pause frame support if an interface is running low on input queue buffers. And, the PHY chip supports line-level signaling like PAM (a modulation scheme).
Go WIDE SCREEN TO SEE DIAGRAMS BELOW.
IE: (SoC or CPU or peripheral interface)
<separate PHY and MAC and shared MDIO/MDC access of PHY(SFP) and MAC>
SoC -----SGMII/RGMII---- MAC chip (can be a switch chip with VLAN support) --- PHY chip for magnetics etc (SFP).
SoC ----- MDIO/MDC ----------------------------------------------------------- PHY
(controlling PHY-related things like speed/FDX/HDX/Auto Negotiate)
SoC ----- MDIO/MDC ----- MAC chip
(controlling VLAN tagging, reading MAC-related data - overruns/runts and time stamps (for PTP) if the chip is 1588 capable)
The MDIO/MDC supports addressing different devices attached to the MDIO/MDC data bus.
OR
SoC ---- SGMII/RGMII ---- MAC chip w/Magnetics --- Cable (in this case magnetics and their control is on the MAC chip i.e. Speed, Duplex to control PAM signals etc)
SoC ---- MDIO/MDC ------- MAC chip
The MDIO/MDC control bus essentially gives the user access to Clause 22 and Clause 45 registers used to control the MAC/PHY or a MAC and PHY chip interface to the actual cable.
SFP allows the user to plug in different interfaces (telco etc) your PC only will have a RJ485 connector with magnetics built in. But telco's use SFP to convert to Optical or Electrical interfaces between their different pieces of equipment. Optical is usually preferred due to noise immunity, distance of transmission, and electrical isolation.