For those unfamiliar with IDL (interface description language), it abstracts data description for use across platforms (java, c, c++, etc). My project has dependencies Foo.c, Foo.h, FooHelper.c, and FooHelper.h which are generated from Foo.idl. How do I run an arbitrary command when Foo.idl changes, but still include Foo.c, FooHelper.c, in the build process?
My current attempts add a rule to the Makefile.am -- the hope is that the rule is copied over to the generated Makefile.
I have tried:
Foo.idl : Foo.idl
${the_generate_command}
and then added Foo.idl to my_program_SOURCES but it doesn't run the_generate_command when building.
I have had success generating from the IDL with
Foo.c Foo.h FooHelper.h FooHelper.c : Foo.idl
${the_generate_command}
But it won't add Foo.c, FooHelper.c to the compile process, so they're never built, just generated by the_generate_command!
All the code (including the idl) is in $PROJECT_DIR/src.
rq's answer is almost correct, but misses a couple of subtleties. Try this:
bin_PROGRAMS = myprogram
myprogram_SOURCES = Foo.c Foo.h FooHelper.h FooHelper.c $(OTHER_SOURCES)
BUILT_SOURCES = Foo.c Foo.h FooHelper.h FooHelper.c
EXTRA_DIST = Foo.idl
MAINTAINERCLEANFILES = Foo.c Foo.h FooHelper.h FooHelper.c
Foo.c: Foo.idl
$(THE_GENERATE_COMMAND)
Foo.h FooHelper.h FooHelper.c: Foo.c
#if test -f $#; then \
touch $#; \
else \
## Recover from the removal of $#
rm -rf $<; \
$(MAKE) $(AM_MAKEFLAGS) $<; \
fi
The additional rules to "generate" Foo.h, FooHelper.h and FooHelper.c from Foo.c ensure that parallel builds won't try and run $(THE_GENERATE_COMMAND) twice. It is an idiom detailed in the Automake manual which will work for parallel builds. There is still a little fragility here: if the user removes (say) FooHelper.h and FooHelper.c and starts a parallel make, it may run the $(MAKE) $(AM_MAKEFLAGS) $< recovery part of the rule multiple times in parallel. As the manual says, this race can only going to happen if the user manually mutilates the build tree, and even then it's nothing a make clean; make cannot fix.
The BUILT_SOURCES line ensures that Foo.c, Foo.h, FooHelper.h and FooHelper.c are built before trying to build myprogram (see this section of the Automake manual to see why just adding them to myprog_SOURCES is insufficient). The EXTRA_DIST variable ensures that the .idl file will be captured by make dist (reference).
MAINTAINERCLEANFILES specifies additional files to delete when running make maintainer-clean; this is to comply with the GNU Makefile Standards. See also the variable's description in the Automake manual.
Related
I have a makefile that I've changed up a bit here to look more generalized
.PHONY:
bash hash.sh
all: .PHONY lab tests.zip
lab: .PHONY lab.cpp
g++ -o lab lab.cpp -g -Wall -std=c++11
tests.zip:
curl -L -O https://url/tests.zip
unzip tests.zip
tests: .PHONY lab tests.zip
bash scripts/test.bash lab.cpp
clean:
rm -rf scripts tests bitset-tests.zip
I am a TA for an entry level computer science course at my university, and I've created a makefile here for my students to use to compile and test their code seamlessly.
One thing I want to do though is to have the makefile update itself every time the remote repository has a new version of it. I know I could just have them update the file themselves, but my job is to make the students focus less on setting things up and more on just coding for now, since it's entry level. So for the purposes of this, I'm sticking with the idea I have.
Currently, I'm achieving this with a script hash.sh which fetches a hash of the makefile from the repo, and compares it to a hash of the makefile in the student's directory. If the hashes don't match, then the updated makefile is fetched and replaces the old one. This is done in the .PHONY recipe. I should also mention that I don't want to add a recipe that updates it like make update, because again I want the process to be seamless. You'd be surprised how many students wouldn't utilize that feature, so I want to build it into the ones they will use for sure.
Is there a better method for this, or am I doing something wrong with this one?
Thomas has the right idea, but you can't use .PHONY here because it would means the makefile is ALWAYS out of date; make knows this so it doesn't re-exec itself if its included makefile is marked .PHONY.
You need to create a way for make to know if the makefile was changed since the last time it was run locally. I recommend you do it like this:
<normal makefile here>
Makefile: FORCE
curl https://.../Makefile -o Makefile.tmp
cmp -s Makefile Makefile.tmp && rm -f Makefile.tmp || mv -f Makefile.tmp Makefile
FORCE:
What does this do? First it uses a FORCE target which is an old-school way to emulate a .PHONY target, which is always out of date, without actually using .PHONY (which as I mentioned above, is handled specially by GNU make in this situation).
Second it retrieves the Makefile but only updates the local makefile if it has changed. If it hasn't changed, it doesn't update the local makefile and so make won't re-exec itself.
The whole stuff with fetching a hash sounds overly complicated. If you're going to do a fetch anyway, why not unconditionally fetch the entire makefile? It saves a network round trip, which is probably the limiting factor; the actual data is probably just a few kB anyway.
If you're using curl, notice the --time-cond option, for example:
curl https://... --time-cond Makefile -o Makefile
This will only fetch and update the Makefile if it's newer than the mtime of the current file. It works by sending an If-Modified-Since HTTP header, so you'll need some cooperation from the server for this to work reliably.
If using GNU make, you can use another neat trick: Remake the makefile itself. If you have a rule whose target is Makefile, it will be executed before anything else happens, and make will re-read the updated Makefile before proceeding:
.PHONY: Makefile
Makefile:
curl https://... --time-cond Makefile -o Makefile
Note that this will lead to infinite loops if for whatever reason the --time-cond leads to an unconditional update, so it wouldn't hurt to guard against that:
.PHONY: Makefile
Makefile:
[[ ! -v MAKE_RESTARTS ]] && \
curl https://... --time-cond Makefile -o Makefile
A common Makefile for automatically prereq, looks like:
SRCS := $(wildcard *.c)
OBJS := $(SRCS:%.c=%.o)
DEPS := $(OBJS:%.o=%.d)
$(OBJS): %.o: %.c
$(CC) $(CFLAGS) -c -o $# $<
include $(DEPS)
$(DEPS): %.d: %.c
xxx
the first time, build ok, the generated .d file like this:
config.o config.d: config.c config.h
then I rename config.h to config2.h, and modify config.c:
-#include "config.h"
+#include "config2.h"
make again, Makefile generate error:
make[1]: *** No rule to make target 'config.h', needed by 'config.d'
because config.d depends config.h, How can I modify my Makefile to fix this rename problem.
Pretty simple really. Your .d file needs this additional line:
config.h:
Now when make discovers config.h doesn't exist,
it will run the non-existent recipe and happily believe it has created config.h. Then it carries on.
The manual says:
If a rule has no prerequisites or recipe, and the target of the rule is a nonexistent file, then make imagines this target to have been updated whenever its rule is run.
How to we get this extra line?
Back in the day you would run a perl one-liner over the newly created .d file. Nowadays, for modern gcc variants, just add -MP to the compiler command-line.
-MP This option instructs CPP to add a phony target for each dependency other than the main file, causing each to depend on nothing. These dummy rules work around errors make gives if you remove header files without updating the Makefile to match.
Job's a good 'un.
I have a following scenario in my build system.
1. 1000 makefiles in src directories
2. There is common.make file being included for all 1000 makefiles
3. links were created for makefiles and sources in object directory from source directory. Hence all makefiles and many more scripts inside makefile are written in such a way as it exists in build directory.
4. obj directory is the dynamic location.
5. Now I removed all links.no more links in object directory.
6. I want to execute all makefiles in source directory where I expect to change the object directory (dynamic directory name) before executing. (I can't use make -C here, because I do not know what directory to change). I can set VPATH for finding sources.
7. I want to make use common.make to change the directory dynamically, but whatever cd, $(shell cd ...) I do in common.make is not reflected in main Makefile.
8. If I do not do this, I will end up in modifying all 1000 makefiles. I do not want to do this.
Please let me know the best of way of doing it. In simple words, I want to change the directory (through common.make) before executing my 1000 makefiles,
I expect common.make to do the following.
1) save srcpath = current path (current path is source directory)
2) Change to output directory (Directory name is dynamic here).
3) set VPATH=srcpath
4) now any makefile in source directory can make use of common.make to compile and have the binaries and objects in output directory.
# This is one of the sample Makefile. I have shortened this file. All makefiles are not using the same names like SRCS, CMDSRCS. It would be different.
# this is existing makefile. Source location /home/user/project/src/mod1/lib/resmgr>make BD=100. I want the output to
# /home/user/project/build/swout100/mod1/lib/resmgr/*. common.make (common make) might validate the argument BD here. BD=101 is not allowed.
# We can force the user to do make -C /home/user/project/build/swout100/mod1/lib/resmgr (no BD validation here. user should know what directory to go).
# I would expect common.make would help the user as utility makefile
TOPDIR = ../../..
MAKEDIR = $(TOPDIR)/make
include $(MAKEDIR)/common.make # It is included in most makefiles. This can be treated as common makefile. I thought of modifying common.make
include ........ #(More includes here)
TARGET = resmgrd
CMDSRCS = resmgr_cli.c \
resmgrlogshow.c \
# more source files here
CMDOBJS = $(CMDSRCS:.c=.o)
CMDHNDLR = resmgrcmd
#... CFLAGS here and library flags here
MDSRC = main.c
SRCS = resmgr.c \
# more source files here
HDRS = resmgr.h
MDOBJ = $(MDSRC:.c=.o)
OBJS = $(SRCS:.c=.o)
$(OBJS) $(MDOBJ) $(CMDOBJS): $(HDRS)
DEPENDSRCS = $(MDSRC) $(SRCS) $(CMDSRCS)
ST_LIBS = $(DEVOSLIBSRC)/apixdr/libapixdr.a
$(TARGET): $(MDOBJ) $(OBJS)
$(CC) $(LDFLAGS) -o $# $^ $(LDLIBS) $(ST_LIBS)
$(CMDHNDLR): $(CMDOBJS)
$(CC) $(LDFLAGS) -o $# $^ $(DEVOSLIBS) $(IPCLIB) $(KILIB) $(MIAUXLIB) \
$(RESMGRLIB) $(RBACLIB)
install:: install-server
install-server: $(TARGET) $(TARGET).options $(DEVOSSBINDIR) $(DEVOSCONFDIR)
$(INSTALL) -m 755 $(TARGET) $(DEVOSSBINDIR)
install-commands: $(DEVOSBINDIR)/$(CMDHNDLR) \
install-admin-cmds install-user-cmds
clean::
$(RM) $(OBJS) $(TARGET) $(SCRIPTS) $(RAWMAN) $(CMDHNDLR) $(ZIPMAN)
I found an answer to my question.
http://make.paulandlesley.org/multi-arch.html
I'm working on some bare-metal embedded code that runs on ARM, and thus has to deal with the whole ARM vs. THUMB mode distinction. The current build system uses static pattern rules to determine whether to compile files in ARM or THUMB mode.
$(ACOBJS) : %.o : %.c
#echo
$(CC) -c $(CFLAGS) $(AOPT) -I . $(IINCDIR) $< -o $#
$(TCOBJS) : %.o : %.c
#echo
$(CC) -c $(CFLAGS) $(TOPT) -I . $(IINCDIR) $< -o $#
Where ACOBJS is a list of output objects that should be in ARM mode and the same for TCOBJS and Thumb mode. These lists are created from the list of sources in the usual manner of
ACOBJS = $(ACSRC:.c=.o)
TCOBJS = $(TCSRC:.c=.o)
Currently this results in the object files from the build being strewn about the source tree, which I don't particularly desire. I've been trying to set this up for out of tree builds but haven't been able to get this to work. I don't necessarily need to get full out of tree builds working, but I would like to at least be able to use an output directory under which all the intermediate files end up going. What is the best strategy to achieve this under these constraints?
One option I'm considering is using either automake or the whole autotools toolchain to build a makefile. This would seem to support creating the type of makefile I want, but seems like overkill. It also seems like there would be an inherent impedance mismatch between autotools, which is designed for portable builds, and bare-metal embedded systems, where things like host tuple are dictated by the target micro.
This is a bit old but I was just trying to do the same thing this was the first google hit. I thought it was worth sharing another approach since neither answer is convenient if you're not using autotools and want to be able to build in any directory with a single command and later just blow away that directory.
Here's an example of a Makefile that refers to files relative to the directory containing the Makefile.
MAKEFILE_DIR := $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST))))
MFD := $(MAKEFILE_DIR)
CXX=g++
CXXFLAGS=-std=c++14 -Wall -Wextra -pedantic -c
test: test.o adjacency_pointers_graph.o
$(CXX) $^ -o $#
%.o: $(MFD)/%.cpp $(MFD)/adjacency_pointers_graph.h
$(CXX) $(CXXFLAGS) $< -o $#
Then to do an sort of source build:
mkdir build
cd build
make -f ../Makefile
Considering/assuming you don't care about portability and are using GNU make, you can use the VPATH feature:
Create the directory where you want to do your build.
Create a 'Makefile' in that directory with (approximately) the following contents:
path_to_source = ..
VPATH = $(path_to_source)
include $(path_to_source)/Makefile
Change the path_to_source variable to point to the root of your source tree.
Additionally you probably need to tweak your original Makefile to make sure that it supports the out of source build. For example, you can't reference to prerequisites from your build rules and instead must use $^ and $<. (See GNU make - Writing Recipes with Directory Search) You might also need to modify the vpath-makefile. For example: adding CFLAGS+=-I$(path_to_source) might be useful.
Also note that if a file is in both your source and build directory, make will use the file in your build directory.
On automake
If you use automake, you're pretty much using the entire autotools. automake cannot work without autoconf.
The Makefiles generated by automake support out-of-source builds and cross-compilation, so you should be able to create subdirectories arm/ and thumb/ and run ../configure --host=arm-host-prefix in arm/ and run ../configure --host=thumb-host-prefix in thumb/. (I don't know the actual host tuples that you'd use for each compiler.)
Using GNU make
Since you're using GNUMake, you could do something like this:
ACOBJS := $(addprefix arm/,$(ACSRC:.c=.o))
TCOBJS := $(addprefix thumb/,$(TCSRC:.c=.o))
Use something like this answer to ensure that the arm/ and thumb/ directories (and any subdirectories) exist.
I am using cmake to build my project. For UNIX, I would like to type make from my project's root directory, and have cmake invoked to create the proper Makefiles (if they don't exist yet) and then build my project. I would like the cmake "internal" files (object files, cmake internal Makefiles, etc.) to be hidden (e.g. put in a .build directory) so it doesn't clutter my project directory.
My project has several sub-projects (in particular, a library, a user executable, and a unit test executable). I would like Makefiles (i.e. I type make and this happens) for each sub-project to execute cmake (as above) and build only that sub-project (with dependencies, so the library would be built from the executables' Makefiles, if needed). The resulting binary (.so library or executable) should be in the sub-project's directory.
I made a Makefile which does the main project bit somewhat well, though it feels somewhat hackish. I can't build specific targets using it, because my Makefile simply calls make in cmake's build directory.
Note that because the library is a sole dependency (and probably doesn't need to be build manually, and because I'm lazy) I omitted it in my Makefile.
BUILD_DIR := .build
.PHONY: all clean project-gui ${BUILD_DIR}/Makefile
all: project-gui project-test
clean:
#([ -d ${BUILD_DIR} ] && make -C ${BUILD_DIR} clean && rm -r ${BUILD_DIR}) || echo Nothing to clean
project-gui: ${BUILD_DIR}/Makefile
#make -C ${BUILD_DIR} project-gui
#cp ${BUILD_DIR}/project-gui/project-gui $#
project-test: ${BUILD_DIR}/Makefile
#make -C ${BUILD_DIR} project-test
#cp ${BUILD_DIR}/project-test/project-test $#
${BUILD_DIR}/Makefile:
#[ -d ${BUILD_DIR} ] || mkdir -p ${BUILD_DIR}
#[ -f ${BUILD_DIR}/Makefile ] || (cd ${BUILD_DIR} && cmake ${CMAKE_OPTS} ..)
If it helps, here's my project structure (if this is "wrong" please tell me -- I'm still learning cmake):
project/
project/CMakeLists.txt
project/common.cmake
project/Makefile -- see Makefile above for this; should be replaced with something better, building libproject, project-gui, and project-test
project/libproject/
project/libproject/CMakeLists.txt
project/libproject/libproject.so -- after build
project/libproject/Makefile -- doesn't exist yet; should build libproject only
project/libproject/source/
project/libproject/include/
project/project-gui/
project/project-gui/CMakeLists.txt
project/project-gui/Makefile -- doesn't exist yet; should build libproject then project-gui
project/project-gui/source/
project/project-gui/include/
project/project-test/
project/project-test/CMakeLists.txt
project/project-test/Makefile -- doesn't exist yet; should build libproject then project-test
project/project-test/source/
project/project-test/include/
If you haven't caught on yet, I'm basically looking for a way to build the project and sub-projects as if cmake wasn't there: as if my project consisted of only Makefiles. Can this be done? Is the solution elegant, or messy? Should I be trying to do something else instead?
Thanks!
If cmake is generating the makefiles, you can simply include the generated makefile in the master makefile, eg
# makefile
all: # Default
include $GENERATED
$GENERATED:$CMAKEFILE
# Generate the makefile here`
The included files are generated then make is restarted with the new included files. The included files should detail the targets, etc.
You should be able to change the location of used files using the vpath directive, see e.g. the Gnu make manual,
vpath %.o project/.build
else the tedious way is to rewrite the rules making note of the necessary directory.
Ed:
Perhaps we shouldn't use a flat makefile.
Try something like:
# makefile
all: gui test
clean:
$(MAKE) -f $(GUI-MAKE) clean
$(MAKE) -f $(TEST-MAKE) clean
gui:$(GUI-MAKE)
$(MAKE) -f $(GUI-MAKE) all
$(GUI-MAKE):$(GUI-CMAKE)
# Generate
# Same for test
This should work if the $(MAKE) -f $(GUI-MAKE) all command works on the command line, and we've hidden cmake in the generating target. You would have to copy any other targets to the master makefile as well, and take care running make in parallel.
Propagating object files through should involve something like
%.o:$(GUI-MAKE)
$(MAKE) -f $(GUI-MAKE) $#
although you'll probably get errors trying to make test objects